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| Application Note V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 32-Bit Single-Chip Microcontrollers PCI Host Bridge Macro V850E/MA1: PD703103A PD703108 PD703105A PD703106A PD703106A(A) PD703107A PD703107A(A) PD70F3107A PD70F3107A(A) V850E/MA2: V850E/MA3: PD703131A PD703111A PD703131AY PD703132A PD703132AY PD703133A PD703133AY PD703134A PD703134AY PD70F3134A PD70F3134AY V850E/ME2: Document No. U17121EJ1V1AN00 (1st edition) Date Published September 2004 N CP(K) 2004 Printed in Japan [MEMO] 2 Application Note U17121EJ1V1AN NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Application Note U17121EJ1V1AN 3 The copyright of the PCI host bridge macro described in this document is held by the System Interface Module Development Department, Device Solutions Division, NEC Engineering, Ltd. Green Hills Software and MULTI are trademarks of Green Hills Software, Inc. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of March, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 Application Note U17121EJ1V1AN Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65030 * Sucursal en Espana NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J04.1 Application Note U17121EJ1V1AN 5 INTRODUCTION Readers This application note is intended for users who wish to understand the functions of the V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2, and PCI bus to design application systems using these products. Purpose The purpose of this application note is to help the user understand the PCI host bridge macro and its composition using the V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2, and PCI host bridge macro as a system example. Organization This application note is broadly divided into the following sections. * Overview of each product * Overview of PCI host bridge macro * Specifications of PCI host bridge macro * Configuration examples of FPGA integration * Application examples How to Read This Manual It is assumed that the readers of this application note have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. For details of the hardware functions and electrical specifications of the V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 Refer to the Hardware User's Manual of each product. For details of the instruction functions of the V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 Refer to the V850E1 Architecture User's Manual. Conventions Data significance: Higher digits on the left and lower digits on the right signal name) Active low representation: xxx (overscore over pin or signal name) or /xxx ("/" before Memory map address: Note: Caution: Remark: Numeric representation: Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo) ... 210 = 1,024 M (mega) ... 220 = 1,0242 G (giga) ... 230 = 1,0243 6 Application Note U17121EJ1V1AN Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 Document Name V850E1 Architecture User's Manual V850E/MA1 Hardware User's Manual V850E/MA1 Hardware Application Note V850E/MA2 Hardware User's Manual V850E/MA3 Hardware User's Manual V850E/ME2 Hardware User's Manual V850E/ME2 Hardware Application Note V850E/ME2 USB Function Driver Application Note V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 PCI Host Bridge Macro Application Note Document No. U14559E U14359E U15179E U14980E U16397E U16031E U16794E U17069E This manual Documents related to development tools (user's manuals) Document Name IE-V850E-MC, IE-V850E-MC-A In-Circuit Emulator IE-703107-MC-EM1 In-Circuit Emulator Option Board IE-V850E1-CD-NW PCMCIA Card Type On-Chip Debug Emulator CA850 Ver.2.50 C Compiler Package Operation C Language Assembly Language PM plus Ver.5.20 ID850 Ver.2.50 Integrated Debugger ID850NW Ver.2.51 Integrated Debugger SM850 Ver.2.40 System Simulator SM850 Ver.2.00 or Later System Simulator RX850 Ver.3.13 or Later Real-Time OS Operation Operation Operation External Part User Open Interface Specifications Basics Installation Technical RX850 Pro Ver.3.15 Real-Time OS Basics Installation Technical RD850 Ver.3.01 Task Debugger RD850 Pro Ver.3.01 Task Debugger AZ850 Ver.3.10 System Performance Analyzer PG-FP4 Flash Memory Programmer Document No. U14487E U14481E U16647E U16053E U16054E U16042E U16934E U16217E U16454E U15182E U14873E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U15260E Application Note U17121EJ1V1AN 7 CONTENTS CHAPTER 1 OVERVIEW OF EACH PRODUCT..................................................................................10 1.1 Outline ...........................................................................................................................................10 1.2 Features.........................................................................................................................................11 1.3 Ordering Information....................................................................................................................12 1.4 Pin Configuration..........................................................................................................................14 1.5 Internal Block Diagram ................................................................................................................25 CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO..............................................................29 2.1 Outline ...........................................................................................................................................29 2.2 Features.........................................................................................................................................30 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO ...................................................31 3.1 Internal Blocks of PCI Host Bridge Macro .................................................................................31 3.2 Relationship Between Internal Blocks and Signals ..................................................................32 3.3 Pin Functions ................................................................................................................................33 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 External bus slave interface pins .......................................................................................................33 SDRAM bus interface pins .................................................................................................................33 PCI bus interface pins ........................................................................................................................34 PCI_CONFIG_DATA register.............................................................................................................35 PCI_CONFIG_ADD register...............................................................................................................36 PCI_CONTROL register.....................................................................................................................37 PCI_IO_BASE register.......................................................................................................................38 PCI_MEM_BASE register ..................................................................................................................38 PCI_INT_CTL register........................................................................................................................39 PCI_ERR_ADD register .....................................................................................................................40 SYSTEM_MEM_BASE register .........................................................................................................41 SYSTEM_MEM_RANGE register ......................................................................................................41 3.4 Registers .......................................................................................................................................35 3.4.10 SDRAM_CTL register ........................................................................................................................42 3.5 3.6 3.7 3.8 Address Map .................................................................................................................................44 Initializing PCI Host Bridge Macro ..............................................................................................45 Bus Width of External Bus Interface ..........................................................................................46 Timing ............................................................................................................................................47 3.8.1 3.8.2 External bus interface timing..............................................................................................................47 PCI bus interface timing .....................................................................................................................50 CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION..........................................57 4.1 Conditions for Configuration Examples of FPGA Integration .................................................57 4.2 Points to Remember When Creating Top Layer of FPGA ........................................................57 4.3 Reference Diagram for FPGA Top Connection .........................................................................58 4.4 FPGA Top Pin Functions .............................................................................................................59 4.4.1 4.4.2 4.4.3 CPU bus slave interface pins .............................................................................................................59 SDRAM bus interface pins .................................................................................................................59 PCI bus interface pins ........................................................................................................................60 4.5 FPGA Top Pin Configuration.......................................................................................................61 8 Application Note U17121EJ1V1AN 4.5.1 4.5.2 4.5.3 4.5.4 4.6.1 4.6.2 4.6.3 Internal connection diagram of external bus interface ....................................................................... 61 Internal connection diagram of PCI bus interface .............................................................................. 62 External connection diagram of external bus interface (example of connection with V850E/ME2).... 63 External connection diagram of PCI bus interface ............................................................................. 64 FPGA fitting design............................................................................................................................ 65 PCI bus interface timing parameters (as constraint of PCI CLK = 33 MHz)....................................... 65 SDRAM interface timing .................................................................................................................... 66 4.6 Cautions on Designing FPGA .....................................................................................................65 CHAPTER 5 APPLICATION EXAMPLES..............................................................................................67 5.1 Block Diagram of Evaluation Board ...........................................................................................67 5.2 Specifications of Evaluation Board............................................................................................68 5.3 Example of Evaluation Board Connection Circuit ....................................................................69 5.4 Evaluation Board Memory Space ...............................................................................................70 5.5 Sample Program Examples .........................................................................................................72 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 Development tools ............................................................................................................................. 72 Program configuration ....................................................................................................................... 72 V850E/ME2 PCI host bridge macro initialization sample program list ............................................... 73 PCI configuration space access sample program list ........................................................................ 76 IDE HDD access sample program list................................................................................................ 79 Application Note U17121EJ1V1AN 9 CHAPTER 1 OVERVIEW OF EACH PRODUCT The V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 are products in NEC Electronics' V850 Series of single-chip microcontrollers. This chapter gives a simple outline of each product. 1.1 Outline The V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 are 32-bit single-chip microcontrollers that integrate the V850E1 CPU, which is a 32-bit RISC-type CPU core for ASIC, newly developed as the CPU core central to system LSI in the current age of system-on-chip. These devices incorporate memory and various peripheral functions such as memory controllers, a DMA controller, timer/counters, serial interfaces, and an A/D converter for realizing high-capacity data processing and sophisticated real-time control. 10 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.2 Features Commercial Name Maximum operating frequency Internal memory (KB) Mask ROM Flash memory RAM 4 V850E/MA1 50 MHz - 128 - 10 256 - 256 V850E/MA2 40 MHz - - 4 - Separate 26 bits 8/16 bits Separate 25 bits 8/16 bits 4 SDRAM, SRAM, etc. 4 (4) 27 25 to 50 ns (40 MHz) 75 ns (40 MHz) 2 ch - - 4 ch - - 1 ch 1 ch 2 ch - 8 ch - 4 ch 9 106 - PWM x 2 ch 3.0 to 3.6 V 528 mW 416 mW 4 ch 5 74 - - 4 ch - 2 ch - 2 V850E/MA3 80 MHz 256 - 16 32 16 512 - 512 32 V850E/ME2 150 MHz - - Instruction RAM: 128 Data RAM: 16 Instruction cache: 8 Cache (KB) External bus Bus type Address bus Data bus Separate/multiplexed 26 bits 8/16 bits 8 Separate 26 bits 16/32 bits 8 Chip select signals 8 Memory controller Interrupts External Internal DSP function 16-bit timer 32 x 32 64 Note 1 SDRAM, EDO DRAM, SRAM, etc. 17 (17) 41 20 to 40 ns (50 MHz) 26 (26) 49 12.5 to 25 ns (80 MHz) 37.5 ns (80 MHz) - - - 3 ch 1 ch 4 ch - - - - 3 ch 1 ch 8 ch 2 ch 4 ch 11 101 Provided (RUN, break) Note 2 40 (31) 59 6.7 to 13.3 ns (150 MHz) 20 ns (150 MHz) 6 ch - - 4 ch 2 ch - - - 1 ch 1 ch 1 ch - 8 ch - 4 ch 7 77 Provided (RUN, break, trace) 32 x 32 + 32 32 60 ns (50 MHz) TMC TMP TMQ Interval timer Up/down counter 4 ch 4 ch 1 ch 1 ch Watchdog timer Serial CSI interface UART CSI/UART UART/I C 10-bit A/D converter 8-bit D/A converter DMA controller Ports CMOS input CMOS I/O Debug functions Other peripheral functions Power supply voltage Power consumption (mask version TYP.) Package Operating ambient temperature ROM correction function USB function, SSCG, PWM x 2 ch 2.3 to 2.7 V (internal) 3.0 to 3.6 V (external) 575 mW 1.5 V (internal) 3.3 V (external) 200 mW 144-pin LQFP (20 x 20) 100-pin LQFP (14 x 14) 144-pin LQFP (20 x 20) 176-pin LQFP (20 x 20) 161-pin FBGA (13 x 13) 161-pin FBGA (13 x 13) 240-pin FBGA (16 x 16) TA = -40 to +85C TA = -40 to +85C (@133 MHz) TA = -40 to +70C (@150 MHz) Notes 1. The figure in parentheses indicates the number of external interrupts that can release STOP mode. 2. Available only in on-chip I2C products (Y products). Application Note U17121EJ1V1AN 11 CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.3 Ordering Information (1) V850E/MA1 Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) Internal ROM ROMless Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Flash memory (512 KB) Flash memory (512 KB) Flash memory (512 KB) PD703103AGJ-UEN PD703105AGJ-xxx-UEN PD703106AGJ-xxx-UEN PD703106AGJ(A)-xxx-UEN PD703106AF1-xxx-EN4 PD703107AGJ-xxx-UEN PD703107AGJ(A)-xxx-UEN PD703107AF1-xxx-EN4 PD70F3107AGJ-UEN PD70F3107AGJ(A)-UEN PD70F3107AF1-EN4 (2) V850E/MA2 Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) Internal ROM ROMless PD703108GC-8EU 12 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT (3) V850E/MA3 Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic FBGA (13 x 13) Internal ROM Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (512 KB) Mask ROM (512 KB) Mask ROM (512 KB) Mask ROM (512 KB) Mask ROM (512 KB) Mask ROM (512 KB) Mask ROM (512 KB) Mask ROM (512 KB) Flash memory (512 KB) Flash memory (512 KB) Flash memory (512 KB) Flash memory (512 KB) PD703131AGJ-xxx-UEN PD703131AF1-xxx-EN4 PD703131AYGJ-xxx-UEN PD703131AYF1-xxx-EN4 PD703132AGJ-xxx-UEN PD703132AF1-xxx-EN4 PD703132AYGJ-xxx-UEN PD703132AYF1-xxx-EN4 PD703133AGJ-xxx-UEN PD703133AF1-xxx-EN4 PD703133AYGJ-xxx-UEN PD703133AYF1-xxx-EN4 PD703134AGJ-xxx-UEN PD703134AF1-xxx-EN4 PD703134AYGJ-xxx-UEN PD703134AYF1-xxx-EN4 PD70F3134AGJ-UEN PD70F3134AF1-EN4 PD70F3134AYGJ-UEN PD70F3134AYF1-EN4 (4) V850E/ME2 Maximum Operating Part Number Package 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 176-pin plastic LQFP (fine pitch) (24 x 24) 240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16) Frequency 100 MHz 133 MHz 150 MHz 100 MHz 133 MHz 150 MHz PD703111AGM-10-UEU PD703111AGM-13-UEU PD703111AGM-15-UEU PD703111AF1-10-GA3 PD703111AF1-13-GA3 PD703111AF1-15-GA3 Application Note U17121EJ1V1AN 13 CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.4 Pin Configuration (1) V850E/MA1 * 144-pin plastic LQFP (fine pitch) (20 x 20) PD703103AGJ-UEN PD703105AGJ-xxx-UEN PD703106AGJ-xxx-UEN PD703106AGJ(A)-xxx-UEN PD703107AGJ-xxx-UEN PD703107AGJ(A)-xxx-UEN PD70F3107AGJ-UEN PD70F3107AGJ(A)-UEN Top View PDL15/D15 PAL0/A0 PAL1/A1 PAL2/A2 PAL3/A3 PAL4/A4 PAL5/A5 PAL6/A6 PAL7/A7 VSS VDD PAL8/A8 PAL9/A9 PAL10/A10 PAL11/A11 PAL12/A12 PAL13/A13 PAL14/A14 PAL15/A15 VSS VDD PAH0/A16 PAH1/A17 PAH2/A18 PAH3/A19 PAH4/A20 PAH5/A21 PAH6/A22 PAH7/A23 PAH8/A24 PAH9/A25 VSS VDD PCD0/SDCKE PCD1/SDCLK PCD2/LBE/SDCAS D14/PDL14 D13/PDL13 D12/PDL12 D11/PDL11 D10/PDL10 D9/PDL9 D8/PDL8 VDD VSS D7/PDL7 D6/PDL6 D5/PDL5 D4/PDL4 D3/PDL3 D2/PDL2 D1/PDL1 D0/PDL0 MODE2 (VPP/MODE2) DMARQ3/INTP103/P07 DMARQ2/INTP102/P06 DMARQ1/INTP101/P05 DMARQ0/INTP100/P04 TO00/P03 INTP001/P02 TI000/INTP000/P01 PWM0/P00 VDD VSS DMAAK3/PBD3 DMAAK2/PBD2 DMAAK1/PBD1 DMAAK0/PBD0 TO01/P13 INTP011/P12 TI010/INTP010/P11 PWM1/P10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PCD3/UBE/SDRAS PCS0/CS0 PCS1/CS1/RAS1 PCS2/CS2/IOWR PCS3/CS3/RAS3 PCS4/CS4/RAS4 PCS5/CS5/IORD PCS6/CS6/RAS6 PCS7/CS7 VSS VDD PCT0/LCAS/LWR/LDQM PCT1/UCAS/UWR/UDQM PCT4/RD PCT5/WE PCT6/OE PCT7/BCYST PCM0/WAIT PCM1/CLKOUT/BUSCLK PCM2/HLDAK PCM3/HLDRQ PCM4/REFRQ PCM5/SELFREF P50/INTP030/TI030 P51/INTP031 P52/TO03 VSS VDD P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 Remark Items in parentheses are pin names in the PD70F3107A. 14 VDD VSS TC3/INTP113/P27 TC2/INTP112/P26 TC1/INTP111/P25 TC0/INTP110/P24 TO02/P23 INTP021/P22 TI020/INTP020/P21 NMI/P20 VDD VSS ADTRG/INTP123/P37 INTP122/P36 INTP121/P35 RXD2/INTP120/P34 TXD2/INTP133/P33 SCK2/INTP132/P32 SI2/INTP131/P31 SO2/INTP130/P30 MODE1 MODE0 RESET CKSEL CVDD X2 X1 CVSS SCK1/P45 RXD1/SI1/P44 TXD1/SO1/P43 SCK0/P42 RXD0/SI0/P41 TXD0/SO0/P40 AVDD/AVREF AVSS Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT * 161-pin plastic FBGA (13 x 13) PD703106AF1-xxx-EN4 PD703107AF1-xxx-EN4 PD70F3107AF1-EN4 Top View Bottom View 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A BCDE FGH J K LMNP Index mark PNML K J HGF EDCB A Index mark (1/2) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 D12/PDL12 A0/PAL0 A4/PAL4 VSS A8/PAL8 A13/PAL13 VSS A24/PAH8 VDD LBE/SDCAS/PCD2 UBE/SDRAS/PCD3 - A9/PAL9 A12/PAL12 A15/PAL15 A17/PAH1 - D15/PDL15 A2/PAL2 A5/PAL5 - Name - Pin No. B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 VSS D10/PDL10 D9/PDL9 D13/PDL13 A1/PAL1 A7/PAL7 VDD A11/PAL11 VDD A19/PAH3 A22/PAH6 VSS CS3/RAS3/PCS3 CS2/IOWR/PCS2 - A18/PAH2 A21/PAH5 A25/PAH9 SDCLK/PCD1 CS1/RAS1/PCS1 - - Name Pin No. D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E11 E12 E13 E14 F1 D5/PDL5 D7/PDL7 D8/PDL8 D11/PDL11 - CS6/RAS6/PCS6 CS4/RAS4/PCS4 CS7/PCS7 VSS D2/PDL2 D14/PDL14 A3/PAL3 A6/PAL6 A10/PAL10 A14/PAL14 A16/PAH0 A20/PAH4 A23/PAH7 SDCKE/PCD0 CS0/PCS0 CS5/IORD/PCS5 - Name Application Note U17121EJ1V1AN 15 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2/2) Pin No. F2 F3 F4 F11 F12 F13 F14 G1 G2 G3 G4 G11 G12 G13 G14 H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 D3/PDL3 D4/PDL4 VDD RD/PCT4 VDD LCAS/LWR/LDQM/PCT0 UCAS/UWR/UDQM/PCT1 MODE2 (MODE2/VPP) DMARQ3/INTP103/P07 D0/PDL0 D6/PDL6 WAIT/PCM0 WE/PCT5 BCYST/PCT7 OE/PCT6 DMARQ2/INTP102/P06 DMARQ1/INTP101/P05 DMARQ0/INTP100/P04 D1/PDL1 REFRQ/PCM4 HLDRQ/PCM3 HLDAK/PCM2 CLKOUT/BUSCLK/PCM1 TO00/P03 TI000/INTP000/P01 VDD INTP001/P02 TO03/P52 TI030/INTP030/P50 SELFREF/PCM5 INTP031/P51 PWM0/P00 Name Pin No. K2 K3 K4 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 INTP011/P12 TO01/P13 TC2/INTP112/P26 TI020/INTP020/P21 VSS RXD2/INTP120/P34 MODE0 CKSEL SCK1/P45 TXD0/SO0/P40 VSS DMAAK1/PBD1 DMAAK3/PBD3 ANI1/P71 ANI0/P70 VSS VDD - DMAAK2/PBD2 TI010/INTP010/P11 DMAAK0/PBD0 TO02/P23 VDD INTP122/P36 SI2/INTP131/P31 RESET TXD1/SO1/P43 ANI7/P77 ANI4/P74 ANI3/P73 ANI2/P72 - Name Pin No. M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 RXD1/SI1/P44 RXD0/SI0/P41 - INTP121/P35 SCK2/INTP132/P32 MODE1 CVDD X1 - VDD VSS TC1/INTP111/P25 INTP021/P22 - PWM1/P10 TC3/INTP113/P27 TC0/INTP110/P24 NMI/P20 ADTRG/INTP123/P37 TXD2/INTP133/P33 SO2/INTP130/P30 X2 CVSS SCK0/P42 AVDD/AVREF AVSS - ANI6/P76 ANI5/P75 - - Name Remarks 1. Leave the A1, A5, A10, B1, B14, C1, C14, D14, E5, L1, M1, M14, N1, N14, P5, P11, and P14 pins open. 2. Items in parentheses are pin names in the PD70F3107A. 16 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT (2) V850E/MA2 * 100-pin plastic LQFP (fine pitch) (14 x 14) PD703108GC-8EU Top View PAL2/A2 PAL3/A3 PAL4/A4 PAL5/A5 PAL6/A6 PAL7/A7 VSS VDD PAL8/A8 PAL9/A9 PAL10/A10 PAL11/A11 PAL12/A12 PAL13/A13 PAL14/A14 PAL15/A15 VSS VDD PAH0/A16 PAH1/A17 PAH2/A18 PAH3/A19 PAH4/A20 PAH5/A21 PAH6/A22 TI000/INTP000/P01 DMAAK1/PBD1 DMAAK0/PBD0 INTP011/P12 TI010/INTP010/P11 TC0/INTP110/P24 NMI/P20 VDD VSS MODE1 MODE0 RESET CKSEL CVDD X2 X1 CVSS SCK1/P45 RXD1/SI1/P44 TXD1/SO1/P43 SCK0/P42 RXD0/SI0/P41 TXD0/SO0/P40 AVDD/AREF AVSS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A1/PAL1 A0/PAL0 D15/PDL15 D14/PDL14 D13/PDL13 D12/PDL12 D11/PDL11 D10/PDL10 D9/PDL9 D8/PDL8 VDD VSS D7/PDL7 D6/PDL6 D5/PDL5 D4/PDL4 D3/PDL3 D2/PDL2 D1/PDL1 D0/PDL0 MODE2 DMARQ1/INTP101/P05 DMARQ0/INTP100/P04 TO00/P03 INTP001/P02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PAH7/A23 PAH8/A24 PCD0/SDCKE PCD1/SDCLK PCD2/LBE/SDCAS PCD3/UBE/SDRAS PCS0/CS0 PCS3/CS3 PCS4/CS4 PCS7/CS7 PCT0/LWR/LDQM PCT1/UWR/UDQM PCT4/RD PCT5/WE PCM0/WAIT PCM1/CLKOUT PCM2/HLDAK PCM3/HLDRQ PCM4/REFRQ VSS VDD P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 Application Note U17121EJ1V1AN 17 CHAPTER 1 OVERVIEW OF EACH PRODUCT (3) V850E/MA3 * 144-pin plastic LQFP (fine pitch) (20 x 20) PD703131AGJ-xxx-UEN PD703131AYGJ-xxx-UEN PD703132AGJ-xxx-UEN PD703132AYGJ-xxx-UEN PD703133AGJ-xxx-UEN PD703133AYGJ-xxx-UEN PD703134AGJ-xxx-UEN PD703134AYGJ-xxx-UEN PD70F3134AGJ-UEN PD70F3134AYGJ-UEN Top View PDL15/AD15 PAL0/A0 PAL1/A1 PAL2/A2 PAL3/A3 PAL4/A4 PAL5/A5 PAL6/A6 PAL7/A7 EVSS EVDD PAL8/A8 PAL9/A9 PAL10/A10 PAL11/A11 PAL12/A12 PAL13/A13 PAL14/A14 PAL15/A15 VSS VDD PAH0/A16 PAH1/A17 PAH2/A18 PAH3/A19 PAH4/A20 PAH5/A21 PAH6/A22 PAH7/A23 PAH8/A24 PAH9/A25 EVSS EVDD PCD0/SDCKE PCD1/SDCLK PCD2/SDCAS 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 AD14/PDL14 AD13/PDL13 AD12/PDL12 AD11/PDL11 AD10/PDL10 AD9/PDL9 AD8/PDL8 EVDD EVSS AD7/PDL7 AD6/PDL6 AD5/PDL5 AD4/PDL4 AD3/PDL3 AD2/PDL2 AD1/PDL1 AD0/PDL0 INTP001/TOP01/INTPP01/P01 INTP000/TOP00/EVTP0/TIP0/INTPP00/P00 INTP115/TOQB3/EVTQ/P15 INTP114/TOQB2/TIQ/P14 INTP013/TOQT3/INTPQ3/TOQ3/P13 VDD VSS INTP012/TOQT2/INTPQ2/TOQ2/P12 INTP011/TOQT1/INTPQ1/TOQ1/P11 INTP010/TOQB1/INTPQ0/TOQ0/P10 TDO/TC3/P27 TDI/INTP126/TC2/P26 INTP125/TC1/TIUD10/TO10/P25 INTP124/TC0/P24 TRST INTP004/DMARQ0/TCLR10/INTP11/P04 INTP005/DMARQ1/TCUD10/INTP10/P05 TMS/INTP106/DMARQ2/P06 TCK/INTP107/DMARQ3/P07 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PCD3/SDRAS PCS0/CS0 PCS1/CS1 PCS2/CS2/IOWR PCS3/CS3 PCS4/CS4 PCS5/CS5/IORD PCS6/CS6 PCS7/CS7 EVSS EVDD PCT0/LBE/LWR/LDQM PCT1/UBE/UWR/UDQM PCT4/RD PCT5/WR/WE PCT6/ASTB PCT7/BCYST PCM0/WAIT PCM1/BUSCLK PCM2/HLDAK PCM3/HLDRQ PCM4/REFRQ P50/INTP050/INTPP20/TOP20/EVTP2/TIP2 P51/INTP051/INTPP21/TOP21 P20/NMI P37/INTP137/ADTRG VSS VDD P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 Note SCL and SDA are available only in the PD703131Y, 703132Y, 703133Y, 703134Y, 703137Y, and 70F3134Y. 18 EVDD EVSS DMAAK3/PBD3 DMAAK2/PBD2 DMAAK1/PBD1 DMAAK0/PBD0 INTP022/TOP11/INTPP11/P22 INTP021/TOP10/EVTP1/TIP1/INTPP10/P21 INTP134/RXD3/SCLNote/P34 INTP133/TXD3/SDANote/P33 INTP132/ASCK2/SCK2/P32 INTP131/RXD2/SI2/P31 INTP130/TXD2/SO2/P30 ASCK1/SCK1/P45 RXD1/SI1/P44 TXD1/SO1/P43 ASCK0/SCK0/P42 RXD0/SI0/P41 TXD0/SO0/P40 CVDD X2 X1 CVSS CKSEL PSEL VDD VSS MODE0 MODE1 RESET AVDD1 ANO1/P81 ANO0/P80 AVSS1 AVSS0 AVDD0 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT * 161-pin plastic FBGA (13 x 13) PD703131AF1-EN4 PD703131AYF1-xxx-EN4 PD703132AF1-xxx-EN4 PD703132AYF1-xxx-EN4 PD703133AF1-xxx-EN4 PD703133AYF1-xxx-EN4 PD703134AF1-xxx-EN4 PD703134AYF1-xxx-EN4 PD70F3134AF1-EN4 PD70F3134AYF1-EN4 Top View Bottom View 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A BCDE FGH J K LMNP Index mark PNML K J HGF EDCB A Index mark (1/2) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 A24/PAH8 EVDD SDCAS/PCD2 SDRAS/PCD3 EVSS AD12/PDL12 A0/PAL0 A4/PAL4 EVSS A8/PAL8 A13/PAL13 EVSS AD15/PDL15 A2/PAL2 A5/PAL5 EVSS A9/PAL9 A12/PAL12 A15/PAL15 A17/PAH1 - Name Pin No. B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 VSS A18/PAH2 A21/PAH5 A25/PAH9 SDCLK/PCD1 CS1/PCS1 EVSS EVSS AD9/PDL9 AD13/PDL13 A1/PAL1 A7/PAL7 EVDD A11/PAL11 VDD A19/PAH3 A22/PAH6 EVSS CS3/PCS3 CS2/IOWR/PCS2 EVSS Name Pin No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E11 E12 CS6/PCS6 CS4/PCS4 EVSS AD10/PDL10 AD14/PDL14 A3/PAL3 A6/PAL6 A10/PAL10 A14/PAL14 A16/PAH0 A20/PAH4 A23/PAH7 SDCKE/PCD0 CS0/PCS0 CS5/IORD/PCS5 EVSS AD5/PDL5 AD7/PDL7 AD8/PDL8 AD11/PDL11 - Name Application Note U17121EJ1V1AN 19 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2/2) Pin No. E13 E14 F1 F2 F3 F4 F11 F12 F13 F14 G1 G2 CS7/PCS7 EVSS AD2/PDL2 AD3/PDL3 AD4/PDL4 EVDD RD/PCT4 EVDD LBE/LWR/LDQM/PCT0 UBE/UWR/UDQM/PCT1 TOP01/INTP001/INTPP01/P01 TOP00/INTP000/EVTP0/TIP0/ INTPP00/P00 G3 G4 G11 G12 G13 G14 H1 H2 H3 H4 AD0/PDL0 AD6/PDL6 WAIT/PCM0 WR/WE/PCT5 BCYST/PCT7 ASTB/PCT6 TOQB3/INTP115/EVTQ/P15 TOQB2/INTP114/TIQ/P14 TOQT3/INTP013/INTPQ3/TOQ3/P13 AD1/PDL1 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 TRST TOP11/INTPP11/INTP022/P22 ASCK2/SCK2/INTP132/P32 ASCK1/SCK1/P45 TXD0/SO0/P40 MODE0 AVDD0 ANI7/P77 ANI4/P74 ANI3/P73 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 EVDD EVSS DMAAK1/PBD1 TOP10/INTPP10/EVTP1/TIP1/ INTP021/P21 H11 H12 H13 REFRQ/PCM4 HLDRQ/PCM3 HLDAK/PCM2 L14 M1 M2 ANI2/P72 EVSS DMARQ1/TCUD10/INTP10/ INTP005/P05 H14 BUSCLK/PCM1 M3 DMARQ0/INTP11/TCLR10/ INTP004/P04 J1 J2 J3 J4 J11 J12 J13 VDD TOQT2/INTP012/INTPQ2/TOQ2/P12 TOQB1/INTP010/INTPQ0/TOQ0/P10 VSS ADTRG/INTP137/P37 TOP21/INTPP21/INTP051/P51 TOP20/INTPP20/EVTP2/TIP2/ INTP050/P50 M4 M5 M6 M7 M8 M9 M10 DMAAK2/PBD2 RXD3/SCL Note Name Pin No. J14 K1 K2 K3 K4 K11 K12 K13 K14 L1 L2 L3 NMI/P20 Name Pin No. M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 EVSS AVSS0 ANI6/P76 ANI5/P75 Name TOQT1/INTP011/INTPQ1/TOQ1/P11 TC3/TDO/P27 TC0/INTP124/P24 TC2/TDI/INTP126/P26 ANI1/P71 ANI0/P70 VSS VDD EVSS TC1/TIUD10/TO10/INTP125/P25 DMARQ2/TMS/INTP106/P06 - DMARQ3/TCK/INTP107/P07 DMAAK3/PBD3 DMAAK0/PBD0 TXD3/SDA Note /INTP133/P33 TXD2/SO2/INTP130/P30 ASCK0/SCK0/P42 VSS X2 CVSS ANO1/P81 AVSS1 AVDD1 - P5 P6 P7 EVSS RXD1/SI1/P44 RXD0/SI0/P41 P8 PSEL P9 P10 P11 P12 P13 P14 CVDD X1 - RESET ANO0/P80 - /INTP134/P34 RXD2/SI2/INTP131/P31 TXD1/SO1/P43 VDD CKSEL MODE1 Note SCL and SDA are available only in the PD703131AY, 703132AY, 703133AY, 703134AY, and 70F3134AY. Leave the A10, E5, M14, N14, P11, and P14 pins open. Remark 20 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT (4) V850E/ME2 * 176-pin plastic LQFP (fine pitch) (24 x 24) PD703111AGM-10-UEU PD703111AGM-13-UEU PD703111AGM-15-UEU Top View P72/DMARQ2/INTPC20/TIC2 P73/DMAAK2/INTPC21 P74/TC2/TOC2 P75/DMARQ3/INTPC30/TIC3 P76/DMAAK3/INTPC31 P77/TC3/TOC3 SSEL0 SSEL1 PLLVSS PLLVDD OSCVSS X2 X1 OSCVDD UVDD UDM UDP P10/UCLK/INTP10 IVSS IVDD PLLSEL P11/SCK0/INTP11 P12/RXD0/SI0 P13/TXD0/SO0 P20/NMI EVSS EVDD P21/RXD1/INTP21 P22/TXD1/INTP22 P23/SCK1/INTP23 P24/SI1/INTP24 P25/SO1/INTP25 DCK DMS DRST DDI DDO TRCCLK TRCEND TRCDATA0 TRCDATA1 IVSS IVDD TRCDATA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 JIT1 JIT0 AVDD AVREFP ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVREFM AVSS MODE1 MODE0 INTP67/TOC1/P67 INTP66/INTPC11/P66 INTP65/TIC1/INTPC10/P65 TOC0/TC1/P55 INTPC01/DMAAK1/P54 INTPC00/TIC0/DMARQ1/P53 INTP52/TC0/P52 INTP51/DMAAK0/P51 INTP50/DMARQ0/P50 IVDD IVSS RESET ADTRG/SELFREF/PCM5 REFRQ/PCM4 HLDRQ/PCM3 HLDAK/PCM2 PCM1 WAIT/PCM0 CS7/PCS7 CS6/PCS6 IORD/CS5/PCS5 EVDD EVSS CS4/PCS4 CS3/PCS3 IOWR/CS2/PCS2 CS1/PCS1 CS0/PCS0 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 TRCDATA3 PDH15/D31/INTPD15/PWM1 PDH14/D30/INTPD14/PWM0 EVSS EVDD PDH13/D29/INTPD13/TIUD11 PDH12/D28/INTPD12/TO11 PDH11/D27/INTPD11/INTP111/TCLR11 PDH10/D26/INTPD10/INTP110/TCUD11 PDH9/D25/INTPD9/TIUD10 PDH8/D24/INTPD8/TO10 PDH7/D23/INTPD7/INTP101/TCLR10 PDH6/D22/INTPD6/INTP100/TCUD10 PDH5/D21/INTPD5/TOC5 PDH4/D20/INTPD4 PDH3/D19/INTPD3 EVSS EVDD PDH2/D18/INTPD2/TOC4 PDH1/D17/INTPD1 PDH0/D16/INTPD0 D15 D14 D13 D12 D11 D10 D9 D8 IVSS IVDD EVSS EVDD D7 D6 D5 D4 D3 D2 D1 D0 SDCKE/PCD0 EVSS EVDD A25/PAH9 A24/PAH8 A23/PAH7 A22/PAH6 A21/PAH5 A20/PAH4 A19/PAH3 A18/PAH2 EVDD EVSS IVDD IVSS A17/PAH1 A16/PAH0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 EVDD EVSS A4 A3 A2 INTPL1/A1/PAL1 INTPL0/A0/PAL0 BCYST/PCT7 WE/WR/PCT5 RD/PCT4 UUDQM/UUBE/UUWR/PCT3 PCT2/ULWR/ULBE/ULDQM PCT1/LUWR/LUBE/LUDQM PCT0/LLWR/LLBE/LLDQM IVDD IVSS SDRAS/PCD3 SDCAS/PCD2 BUSCLK/PCD1 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Application Note U17121EJ1V1AN 21 CHAPTER 1 OVERVIEW OF EACH PRODUCT * 240-pin plastic FBGA (16 x 16) PD703111AF1-10-GA3 PD703111AF1-13-GA3 PD703111AF1-15-GA3 Bottom View 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Top View V U T R PNML K J HG F EDCBA A B CD E FGH J K L MNPRT UV Index mark 22 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT (1/2) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 PCD3/SDRAS IVDD PCT2/ULWR/ULBE/ULDQM PCT5/WE/WR PAL1/INTPL1/A1 EVSS A7 A11 A15 PCS1/CS1 - - PAH8/A24 - A8 A12 PAH0/A16 - - - - PAH5/A21 PAH7/A23 PAH9/A25 - - PCD1/BUSCLK PCD2/SDCAS - PCT3/UUWR/UUBE/UUDQM PCT7/BCYST A2 - A14 IVSS EVDD - EVDD A9 - PCT4/RD - - IVSS PCT0/LLWR/LLBE/LLDQM - Name - Pin No. C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E8 E9 E10 E11 E15 E16 E17 E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 PCS7/CS7 PCM0/WAIT PCM2/HLDAK IVDD EVDD A3 A5 A10 PAH1/A17 PCS4/CS4 EVSS PCS5/CS5/IORD PCS6/CS6 D6 D5 D4 - - A13 EVSS PAH3/A19 - - PCS2/CS2/IOWR PCS3/CS3 EVDD D3 D2 D1 - D0 EVSS PCD0/SDCKE EVDD PCT1/LUWR/LUBE/LUDQM - PAL0/INTPL0/A0 A4 A6 - PCS0/CS0 - IVDD PAH2/A18 PAH4/A20 PAH6/A22 - Name Pin No. G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H5 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L14 L15 L16 L17 L18 M1 MODE0 - P67/INTP67/TOC1 - EVSS PDH3/D19/INTPD3 PDH4/D20/INTPD4 MODE1 - EVDD - D13 - P50/INTP50/DMARQ0 P51/INTP51/DMAAK0 P52/INTP52/TC0 P53/INTPC00/TIC0/DMARQ1 D14 D15 PDH0/D16/INTPD0 PDH1/D17/INTPD1 PDH2/D18/INTPD2/TOC4 P55/TOC0/TC1 P54/INTPC01/DMAAK1 P65/INTP65/INTPC10/TIC1 P66/INTP66/INTPC11 - D11 D12 - IVDD - RESET IVSS - D8 D9 D10 IVSS - EVSS D7 PCM1 PCM3/HLDRQ PCM4/REFRQ PCM5/ADTRG/SELFREF - Name Application Note U17121EJ1V1AN 23 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2/2) Pin No. M2 M3 Name PDH5/D21/INTPD5/TOC5 PDH6/D22/INTPD6/INTP100/ TCUD10 M4 M15 M16 M17 M18 N1 ANI6 AVREFM ANI7 AVSS PDH7/D23/INTPD7/INTP101/ TCLR10 N2 N3 N4 PDH8/D24/INTPD8/TO10 PDH9/D25/INTPD9/TIUD10 PDH10/D26/INTPD10/ INTP110/TCUD11 N15 N16 N17 N18 P1 P2 ANI2 ANI3 ANI4 ANI5 - PDH11/D27/INTPD11/ INTP111/TCLR11 P3 P4 P8 P9 P10 P11 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 DDO ANI0 ANI1 - PDH12/D28/INTPD12/TO11 EVSS PDH14/D30/INTPD14/PWM0 IVDD - UVDD - PDH13/D29/INTPD13/TIUD11 - P23/INTP23/SCK1 P12/SI0/RXD0 - T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 JIT1 JIT0 PDH15/D31/INTPD15/PWM1 - - UDP X1 OSCVSS SSEL1 P75/INTPC30/TIC3/DMARQ3 - DDI - P21/INTP21/RXD1 P20/NMI - V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 PLLVSS P77/TOC3/TC3 P74/TOC2/TC2 - DMS P24/INTP24/SI1 - P13/SO0/TXD0 PLLSEL P10/INTP10/UCLK - - - IVSS TRCDATA0 - R18 T1 T2 T3 T4 T5 TRCDATA1 TRCEND EVDD TRCDATA3 - - U15 U16 U17 U18 V1 V2 TRCDATA2 P76/INTPC31/DMAAK3 P73/INTPC21/DMAAK2 P72/INTPC20/TIC2/DMARQ2 - - R15 R16 R17 AVREFP AVDD - U12 U13 U14 OSCVDD - - - R9 R10 R11 R12 R13 R14 P11/INTP11/SCK0 IVSS UDM X2 PLLVDD SSEL0 U6 U7 U8 U9 U10 U11 DRST P25/INTP25/SO1 P22/INTP22/TXD1 EVSS IVDD - Pin No. R7 R8 DCK EVDD Name Pin No. U4 U5 TRCCLK Name - Remark Leave the A1, A4, A6, A7, A10, A14, A18, B1, B4, B8, B12 to B15, B17, C1, C2, C16, C18, D6, D10, D14, D15, E4, F4, F15, H1, H14, H17, J1, J4, J14, K18, L2, L15, L17, M1, M4, P1, P4, P10, P15, P18, R5, R15, R18, T3, T7, T10, T16, U2 to U4, U11, U13, U14, U18, V1, V5, V8, V12 to V14, and V18 pins open. 24 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT 1.5 Internal Block Diagram (1) V850E/MA1 NMI INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133 INTP000, INTP001, INTP010, INTP011, INTP020, INTP021, INTP030, INTP031 TO00 to TO03 TI000, TI010, TI020, TI030 CPU INTC ROM PC Note 1 BCU MEMC Instruction queue Multiplier (32 x 32 64) DRAMC RPU 32-bit barrel shifter SIO SO0/TXD0 SI0/RXD0 SCK0 SO1/TXD1 SI1/RXD1 SCK1 TXD2 RXD2 SO2 SI2 SCK2 UART2 UART0/CSI0 RAM System registers ALU Note 2 ROMC UART1/CSI1 Generalpurpose registers (32 bits x 32) HLDRQ HLDAK CS0, CS7 CS1/RAS1, CS3/RAS3 CS4/RAS4, CS6/RAS6 CS2/IORD CS5/IOWR SELFREF REFRQ BCYST LBE/SDCAS UBE/SDRAS SDCLK SDCKE WE RD OE UWR/UCAS/UDQM LWR/LCAS/LDQM WAIT A0 to A25 D0 to D15 BUSCLK DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3 DMAC CSI2 PWM0 PWM1 ANI0 to ANI7 AVREF/AVDD AVSS ADTRG PWM0 PWM1 Ports PDL0 to PDL15 PAL0 to PAL15 PAH0 to PAH9 PCS0 to PCS7 PCT0, PCT1, PCT4 to PCT7 PCM0 to PCM5 PCD0 to PCD3 PBD0 to PBD3 P70 to P77 P50 to P52 P40 to P45 P30 to P37 P21 to P27 P20 P10 to P13 P00 to P07 CG CKSEL CLKOUT X1 X2 CVDD CVSS MODE0, MODE1 MODE2/VPPNote 3 RESET VDD VSS ADC System controller Notes 1. PD703103A: ROMless 128 KB (mask ROM) 256 KB (mask ROM) 256 KB (flash memory) 4 KB 10 KB PD703105A, 703106A: PD703107A: PD70F3107A: 2. PD703103A, 703105A: PD703106A, 703107A, 70F3107A: 3. Available only in the PD70F3107A. Application Note U17121EJ1V1AN 25 CHAPTER 1 OVERVIEW OF EACH PRODUCT (2) V850E/MA2 NMI INTP100, INTP101, INTP110 CPU INTC PC BCU MEMC Instruction queue Multiplier (32 x 32 64) SDRAMC INTP000, INTP001, INTP010, INTP011 RPU TO00 TI000, TI010 SIO TXD0/SO0 RXD0/SI0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 UART0/CSI0 RAM 32-bit barrel shifter System registers ALU ROMC 4 KB UART1/CSI1 Generalpurpose registers (32 bits x 32) HLDRQ HLDAK CS0, CS3, CS4, CS7 REFRQ LBE/SDCAS UBE/SDRAS SDCLK SDCKE WE RD UWR/UDQM LWR/LDQM WAIT A0 to A24 D0 to D15 DMAC DMARQ0, DMARQ1 DMAAK0, DMAAK1 TC0 ANI0 to ANI3 AVREF/AVDD AVSS ADC Prescaler Ports PDL0 to PDL15 PAL0 to PAL15 PAH0 to PAH8 PCS0, PCS3, PCS4, PCS7 PCT0, PCT1, PCT4, PCT5 PCM0 to PCM4 PCD0 to PCD3 PBD0, PBD1 P70 to P73 P40 to P45 P24 P20 P11, P12 P01 to P05 CG CKSEL CLKOUT X1 X2 CVDD CVSS MODE0 to MODE2 RESET VDD VSS System controller 26 Application Note U17121EJ1V1AN CHAPTER 1 OVERVIEW OF EACH PRODUCT (3) V850E/MA3 NMI INTP000, INTP001, INTP004, INTP005 INTP010 to INTP013, INTP114, INTP115 INTP021, INTP022, INTP124 to INTP126 INTP130 to INTP134, INTP137, INTP050, INTP051, INTP106, INTP107 TCLR10, TIUD10, TCUD10 INTP10, INTP11 TO10 CPU INTC ROM PC TMENC x 1 ch Note 1 (32 x 32 64) MEMC BCU Instruction queue Multiplier SRAM 32-bit barrel shifter ROM correction TMD x 4 ch ROM System registers ALU SDRAM TIQ, EVTQ, INTPQ0 to INTPQ3 TOQ0 to TOQ3, TOQT1 to TOQT3, TOQB1 to TOQB3 TMQ0 x 1 ch RAM EVTP0 to EVTP2, TIP0 to TIP2, INTPP00, INTPP01 INTPP10, INTPP11, INTPP20, INTPP21 TOP00, TOP01, TOP10, TOP11, TOP20, TOP21 Note 2 Generalpurpose registers (32 bits x 32) WAIT HLDRQ HLDAK BUSCLK A0 to A25 AD0 to AD15 CS0 to CS7 BCYST RD UWR, LWR/UBE, LBE WR ASTB IORD IOWR SDCLK SDCKE SDRAS SDCAS WE LDQM, UDQM REFRQ TMP x 3 ch DMAC WDT DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3 TXD0/SO0 RXD0/SI0 ASCK0/SCK0 TXD1/SO1 RXD1/SI1 ASCK1/SCK1 TXD2/SO2 RXD2/SI2 ASCK2/SCK2 TXD3/SDA Note 3 UARTA0/CSIB0 Ports P00, P01, P04 to P07 P10 to P15 P20 P21, P22, P24 to P27 P30 to P34, P37 P40 to P45 P50, P51 P70 to P77 P80, P81 PAL0 to PAL15 PAH0 to PAH9 PDL0 to PDL15 PCS0 to PCS7 PCT0 to PCT7 PCM0 to PCM4 PCD0 to PCD3 PBD0 to PBD3 UARTA1/CSIB1 CG PLL CKSEL X1 X2 PSEL CVDD CVSS RESET MODE0, MODE1 VDD VSS EVDD EVSS TCK TMS TRST TDO TDI UARTA2/CSIB2 RXD3/SCLNote 3 ANI0 to ANI7 ADTRG AVDD0 AVSS0 UARTA3/I2CNote 3 System controller ADC x 8 ch DCU ANO0, ANO1 AVDD1 AVSS1 DAC x 2 ch Notes 1. PD703131A, 703131AY, 703132A, 703132AY: 256 KB (mask ROM) PD703133A, 703133AY, 703134A, 703134AY: 512 KB (mask ROM) PD70F3134A, 70F3134AY: 512 KB (flash memory) 2. PD703131A, 703131AY, 703133A, 703133AY: 16 KB PD703132A, 703132AY, 703134A, 703134AY, 70F3134A, 70F3134AY: 32 KB 3. Available only in the PD703131AY, 703132AY, 703133AY, 703134AY, 703137AY, and 70F3134AY. Application Note U17121EJ1V1AN 27 CHAPTER 1 OVERVIEW OF EACH PRODUCT (4) V850E/ME2 DRST, DCK, DMS, DDI, DCU DDO, TRCCLK, TRCDATA0 to TRCDATA3, TRCEND NMI INTP10, INTP11 INTP21 to INTP25 INTP50 to INTP52 INTP65 to INTP67 INTPD0 to INTPD15 INTPL0, INTPL1 TCLR10, TCLR11 TIUD10, TIUD11 TCUD10, TCUD11 INTP100, INTP110 INTP101, INTP111 TO10, TO11 TIC0 to TIC3 INTPC00, INTPC01, INTPC10, INTPC11, INTPC20, INTPC21, INTPC30, INTPC31 TOC0 to TOC3 Data RAM CPU MEMC WAIT HLDRQ HLDAK A0 to A25 D0 to D31 BCU INTC PC Multiplier (32 x 32 64) 32-bit barrel shifter Instruction queue SRAM CS0, CS1, CS3, CS4, CS6, CS7 ROM CS2/IOWR CS5/IORD BCYST RD xxWR/xxBE SDRAM WR BUSCLK SDCKE SDRAS SDCAS WE xxDQM REFRQ SELFREF DMARQ0 to DMARQ3 DMA DMAAK0 to DMAAK3 TC0 to TC3 Instruction cache 8 KB ALU TMENC1 Instruction RAM 128 KB System registers TMC 16 KB Generalpurpose registers (32 bits x 32) TOC4, TOC5 TMC BBR TMD SI0/RXD0 SO0/TXD0 SCK0 SI1 SO1 SCK1 RXD1 TXD1 SSEL0, SSEL1 JIT0, JIT1 PLLSEL X1 X2 OSCVDD OSCVSS PLLVDD PLLVSS CSI30/UARTB0 Ports PWM PWM0, PWM1 P10 to P13 P20 P21 to P25 P50 to P55 P65 to P67 P72 to P77 PAL0, PAL1 PAH0 to PAH9 PCD0 to PCD3 PCM0 to PCM5 PCS0 to PCS7 PCT0 to PCT5, PCT7 UARTB1 PDH0 to PDH15 CSI31 ADC ANI0 to ANI7 ADTRG AVREFP, AVREFM AVDD AVSS UDP UDM UCLK UVDD USBF CG System controller RESET MODE0, MODE1 IVDD IVSS EVDD EVSS Remark xx: LL, LU, UL, UU 28 Application Note U17121EJ1V1AN CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO The PCI host bridge macro enables connection of V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 external bus interfaces to the PCI bus interface. This chapter gives an outline of the PCI host bridge macro. 2.1 Outline The PCI host bridge macro is a bridge control macro that connects V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 external bus interfaces (memory controller (MEMC)) to the PCI bus interface. The main memory (SDRAM) can be directly controlled when SDRAM is accessed from a PCI device. Application Note U17121EJ1V1AN 29 CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO 2.2 Features The features of the PCI host bridge macro are as follows. * PCI bus master cycle control PCI configuration register read/write single cycle PCI I/O register read/write single cycle PCI memory read/write single cycle * PCI bus slave cycle control PCI memory read/write cycle (burst transfer up to 8 doublewords (32 bits x 8 bursts)) * PCI bus arbiter control Up to 8 masters can be controlled (one of them is occupied by the PCI host bridge macro) Bus parking master: Limited to PCI host bridge macro/selectable from the last accessed master * PCI bus error processing An error interrupt is generated for master abort/target abort/PERR# reception/SERR# reception The address immediately before an error occurs is retained * PCI bus address conversion control PCI I/O address and PCI memory address registers are supported to convert the physical addresses from the CPU to addresses for the PCI bus * CPU interface control External bus interface (MEMC) Data bus width: 32 bits/16 bits Cycle control by hardware wait control * SDRAM control SDRAM is controlled in response to main memory (SDRAM) access from the PCI device Data bus width: 16 bits/32 bits are supported * PCI clock 33 MHz supported SDRAM control and PCI control clocks are designed to be asynchronous 30 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO This chapter describes the block diagram, signals, register specifications, and operation specifications of the PCI host bridge macro. 3.1 Internal Blocks of PCI Host Bridge Macro The PCI host bridge macro consists of the four blocks shown in Figure 3-1 General Block Diagram of PCI Host Bridge Macro. The functions of each block are described below. (1) LM_BRIDGE: External bus interface master controller This controller is connected to the external bus interface, responds to accesses from the CPU, and issues an access request to the PH_FLIP_BRIDGE block of the PCI bus controller. A bus width of 16 bits or 32 bits can be accessed from the CPU. (2) LS_BRIDGE: External bus interface slave controller This controller responds to accesses from the PH_FLIP_BRIDGE block of the PCI bus controller in response to a memory data transfer request from the PCI device and issues an access request to SDRAMC. (3) SDRAMC: External bus interface SDRAM controller This controller is connected to the SDRAM bus. A memory request from the PCI device via the LS_BRIDGE block is transferred by activating the SDRAM bus. When the bus width of SDRAM is 16 bits, memory cycles of up to 8 bursts are started. When the bus width is 32 bits, memory cycles of up to 4 bursts are started. (4) PH_FLIP_BRIDGE: External bus interface host controller This controller is connected to the PCI bus and operates as the PCI host device. A PCI configuration register read/write cycle, PCI IO register read/write cycle, and PCI memory read/write cycle are started in response to a request from the LM_BRIDGE block. Moreover, a request is issued to the LS_BRIDGE block in response to a memory data transfer request from the PCI device connected to the PCI bus. Figure 3-1. General Block Diagram of PCI Host Bridge Macro PCI host bridge macro External bus interface SDRAM bus interface LM_BRIDGE PH_FLIP_BRIDGE SDRAMC PCI bus interface LS_BRIDGE Application Note U17121EJ1V1AN 31 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.2 Relationship Between Internal Blocks and Signals The I/O signals for each block of the PCI host bridge macro are as follows. Figure 3-2. Blocks and Pin Signals of PCI Host Bridge Macro External bus interface I_SRST_B I_CPU_CS0_B I_CPU_CS1_B I_CPU_CS2_B I_CPU_ADR0 to I_CPU_ADR19 I_CPU_DATA0 to I_CPU_DATA31 O_CPU_DATA0 to O_CPU_DATA31 EN_CPU_DATA I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_WE_B I_CPU_OE_B O_CPU_WAIT_B O_PCIHOST_INT I_MODE16 LM_BRIDGE PCI bus interface I_PCLK O_PCIRST_B I_AD0 to I_AD31 O_AD0 to O_AD31 EN_AD I_CBE0 to I_CBE3 O_CBE0 to O_CBE3 EN_CBE I_FRAME_B O_FRAME_B EN_FRAME I_IRDY_B O_IRDY_B EN_IRDY I_DEVSEL_B LS_BRIDGE PH_FLIP_BRIDGE O_DEVSEL_B EN_DEVSEL SDRAM bus interface O_HOLDREQ_B I_HOLDACK_B I_SDCLK O_SD_DATA0 to O_SD_DATA31 I_SD_DATA0 to I_SD_DATA31 EN_SD_DATA0, EN_SD_DATA1 O_SD_DQM_B0 to O_SD_DQM_B3 O_SD_ADR1 to O_SD_ADR25 O_SD_CKE O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B EN_SD_CTL SDRAMC I_TRDY_B O_TRDY_B EN_TRDY I_STOP_B O_STOP_B EN_STOP I_PAR O_PAR EN_PAR I_PERR_B O_PERR_B EN_PERR I_SERR_B I_REQ_B1 to I_REQ_B7 O_GNT_B1 to O_GNT_B7 32 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.3 Pin Functions The pin functions of each interface are described below. 3.3.1 External bus slave interface pins Pin Name I_SRST_B I_CPU_CS0_B I_CPU_CS1_B I_CPU_CS2_B I_CPU_ADR0 to I_CPU_ADR19 I_CPU_DATA0 to I_CPU_DATA31 O_CPU_DATA0 to O_CPU_DATA31 EN_CPU_DATA I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_WE_B I_CPU_OE_B O_CPU_WAIT_B O_PCIHOST_INT I_MODE16 I/O Input Input Input Input Input Input Output Output Input Input Input Output Output Input System reset input PCI host bridge register chip select input PCI I/O area chip select input PCI memory area chip select input CPU address input CPU data input CPU data output CPU data output enable output CPU data byte enable input CPU write data enable input CPU read data output enable input CPU data wait output PCI host bridge interrupt output CPU data bus width select input Low Low Low Low Low: 32-bit width High: 16-bit width High - Function Low Low Low Low - - - Active 3.3.2 SDRAM bus interface pins Pin Name O_HOLDREQ_B I_HOLDACK_B I_SDCLK O_SD_DATA0 to O_SD_DATA31 I_SD_DATA0 to I_SD_DATA31 EN_SD_DATA0, EN_SD_DATA1 I/O Output Input Input Output Input Output Function SDRAM bus hold request output SDRAM bus hold acknowledge input SDRAM clock input SDRAM data output SDRAM data input SDRAM data enable output Low: Lower 16 bits (O_SD_DATA0 to O_SD_DATA15) High: Higher 16 bits (O_SD_DATA16 to O_SD_DATA31) O_SD_DQM_B0 to O_SD_DQM_B3 O_SD_ADR1 to O_SD_ADR25 O_SD_CKE O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B EN_SD_CTL Output Output Output Output Output Output Output Output SDRAM data mask output SDRAM address output SDRAM clock enable output SDRAM chip select output SDRAM row address strobe output SDRAM column address strobe output SDRAM read/write output SDRAM control signal output enable output (Output buffer enable of O_SD_ADR1 to O_SD_ADR25, O_SD_CKE, O_SD_CS_B, O_SD_RAS_B, O_SD_CAS_B, and O_SD_WR_B pins) High Low Low Low Low High Low - Active Low Low - - - Application Note U17121EJ1V1AN 33 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.3.3 PCI bus interface pins Pin Name I_PCLK O_PCIRST_B I_AD0 to I_AD31 O_AD0 to O_AD31 EN_AD I/O Input Output Input Output Output PCI clock input PCI reset output PCI address/data input PCI address/data output PCI address/data output enable output (Output buffer enable of O_AD0 to O_AD31) I_CBE0 to I_CBE3 O_CBE0 to O_CBE3 EN_CBE Input Output Output PCI command/byte enable input PCI command/byte enable output PCI command/byte enable output enable output (Output buffer enable of O_CBE0 to O_CBE3) I_FRAME_B O_FRAME_B EN_FRAME Input Output Output PCI frame input PCI frame output PCI frame output enable output (Output buffer enable of O_FRAME_B) I_IRDY_B O_IRDY_B EN_IRDY Input Output Output PCI initiator ready input PCI initiator ready output PCI initiator ready output enable output (Output buffer enable of O_IRDY_B) I_DEVSEL_B O_DEVSEL_B EN_DEVSEL Input Output Output PCI device select input PCI device select output PCI device select output enable output (Output buffer enable of O_DEVSEL_B) I_TRDY_B O_TRDY_B EN_TRDY Input Output Output PCI target ready input PCI target ready output PCI target ready output enable output (Output buffer enable of O_TRDY_B) I_STOP_B O_STOP_B EN_STOP Input Output Output PCI stop input PCI stop output PCI stop output enable output (Output buffer enable of O_STOP_B) I_PAR O_PAR EN_PAR Input Output Output PCI parity input PCI parity output PCI parity output enable output (Output buffer enable of O_PAR) I_PERR_B O_PERR_B EN_PERR Input Output Output PCI parity error input PCI parity error output PCI parity error output enable output (Output buffer enable of O_PERR_B) I_SERR_B I_REQ_B1 to I_REQ_B7 O_GNT_B1 to O_GNT_B7 Input Input Output PCI system error input PCI request input PCI grant output Low Low Low Low Low High High - - Low Low High Low Low High Low Low High Low Low High Low Low High Low Low High High Low - - Function Active - 34 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4 Registers The registers of the PCI host bridge macro are listed below. The bit width of all registers is 32 bits. The offset address of each register is the offset value from the base address in the area in which the I_CPU_CS0_B pin becomes active. Offset Address 00H 04H 08H 0CH 10H Register Name PCI_CONFIG_DATA PCI_CONFIG_ADD PCI_CONTROL Reserved PCI_IO_BASE R/W Sets base address of PCI bus I/O space accessed from PCI I/O area on CPU memory map 14H PCI_MEM_BASE R/W Sets base address of PCI bus memory space accessed from PCI memory area on CPU memory map 18H 1CH 20H to 3FH 40H PCI_INT_CTL PCI_ERR_ADD Reserved SYSTEM_MEM_BASE R/W Sets base address of system memory area mapped to PCI bus memory space 44H SYSTEM_MEM_RANGE R/W Sets range of system memory area mapped to PCI bus memory space 48H 4CH to FFH SDRAM_CTL Reserved R/W SDRAM access control R/W R PCI error interrupt control PCI error generation address retention R/W R/W R/W R/W Function PCI configuration register access data setting PCI configuration register access address setting PCI bus control 3.4.1 PCI_CONFIG_DATA register After reset: Undefined 31 CDATA R/W Offset address: 00H 0 Bit Name CDATA R/W R/W Function PCI configuration register write access is executed by writing data to this field, and the data written to this field is written to the access target register. PCI configuration register read access is executed by reading this field, and the data of the access target register is read. Application Note U17121EJ1V1AN 35 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.2 PCI_CONFIG_ADD register After reset: 00000000H 31 CADD R/W Offset address: 04H 0 Bit Name CADD R/W R/W Function Sets PCI configuration register address of access target. (1) How to set PCI_CONFIG_ADD register (a) Type 0 (PCI device) 31 11 10 8 7 2 1 0 IDSEL specification Function number Register number 0 0 IDSEL specification: Selects the IDSEL signal corresponding to the access target PCI device. Because this PCI host bridge macro uses the AD31 to AD11 signals as the IDSEL signal for each PCI device, the AD signal connected to the IDSEL pin of each PCI device is specified in this field. For example, if the AD31 signal is connected to the IDSEL pin of a PCI device, access is enabled by setting bit 31 of CADD to 1. Function number: Register number: Specifies the function number for a multifunction device. Specifies the number of the access target PCI configuration register. (b) Type 1 (PCI-PCI bridge) 31 24 23 16 15 11 10 8 7 2 1 0 Bus number Device number Function number Register number 0 1 Bus number: Device number: Function number: Register number: Specifies the number of the PCI bus connected to the access target PCI device. Specifies the device number of the access target PCI device. Specifies the function number for a multifunction device. Specifies the number of the access target PCI configuration register. 36 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (2) How to access PCI configuration register * Write access Set the access target register address to the PCI_CONFIG_ADD register Write the access target register setting value to the PCI_CONFIG_DATA register * Read access Set the access target register address to the PCI_CONFIG_ADD register Read the PCI_CONFIG_DATA register 3.4.3 PCI_CONTROL register After reset: 07000100H 31 R/W 24 23 Offset address: 08H 17 16 15 PCI_BPMODE 8 7 5 4 PCI_RESET 3 2 TARGET_EN 1 MEM_EN 0 PCI_PARKCNT 0 0 0 0 0 0 0 PCI_REQ 0 0 0 0 Bit Name PCI_PARKCNT R/W R/W Sets the time for shifting to bus parking. Function At the default value, bus parking is performed seven clocks after the bus status becomes IDLE. The counter is started when FRAME# = High and IRDY# = High. PCI_BPMODE R/W Sets the bus parking master. 0: Limited to this macro 1: Master accessed last PCI_REQ R/W Enables/disables the REQ# signal (I_REQ_B1 to I_REQ_B7 pins) from the bus master. Bit 0 of this field (bit 8 of the PCI_CONTROL register) is assigned to the PCI host bridge macro, and is always 1. 0: Disabled 1: Enabled PCI_RESET R/W Sets the reset status of the PCI bus. 0: Reset status 1: Reset released TARGET_EN R/W Sets the operation of the PCI bus target of the PCI host bridge macro. 0: Do not respond to main memory (SDRAM) access from the PCI device 1: Respond to main memory (SDRAM) access from the PCI device MEM_EN R/W Enables/disables access from the CPU to the PCI memory area. 0: Access disabled 1: Access enabled IO_EN R/W Enables/disables access from the CPU to the PCI I/O area. 0: Access disabled 1: Access enabled Application Note U17121EJ1V1AN IO_EN 37 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.4 PCI_IO_BASE register When I/O accessing the PCI bus I/O space via the PCI I/O area (area in which the I_CPU_CS1_B pin becomes active: 64 KB), any area of the 4 GB PCI bus I/O space can be accessed by setting this register. After reset: 00000000H 31 IO_BASE R/W Offset address: 10H 16 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name IO_BASE R/W R/W Function Sets the higher 16 bits (bits 16 to 31) of the PCI bus I/O space base address when accessing the PCI I/O area (area in which the I_CPU_CS1_B pin becomes active) from the CPU. 3.4.5 PCI_MEM_BASE register When memory accessing the PCI bus memory space via the PCI memory area (area in which the I_CPU_CS2_B pin becomes active: 1 MB), any area of the 4 GB PCI bus memory space can be accessed by setting this register. However, because the main memory (SDRAM) is mapped on the PCI bus memory space, do not overlap the area set by the SYSTEM_MEM_BASE register and SYSTEM_MEM_RANGE register described later. After reset: 80000000H 31 M_BASE R/W Offset address: 14H 20 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name M_BASE R/W R/W Function Sets the higher 12 bits (bits 20 to 31) of the PCI bus memory space base address when accessing the PCI memory area (area in which the I_CPU_CS2_B pin becomes active) from the CPU. 38 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.6 PCI_INT_CTL register The PCI_INT_CTL register shows the interrupt sources of the PCI bus error interrupt (O_PCIHOST_INT) and controls masking and clearing of these interrupts. This function is used only for debugging and is not used in normal operation. After reset: 000x0F00H 31 R/W Offset address: 18H 20 19 18 17 16 15 CLR_SERR CLR_PERR CLR_MAB CLR_TAB 12 11 10 MSK_SERR MSK_PERR 9 MSK_MAB 8 MSK_TAB 7 4 3 2 1 MABORT 0 TABORT SERR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name CLR_SERR R/W W Function Clears the PCI bus system error (SERR# reception) interrupt. 1: Cleared CLR_PERR W Clears the PCI bus parity error (PERR# reception) interrupt. 1: Cleared CLR_MAB W Clears the PCI bus master abort interrupt. 1: Cleared CLR_TAB W Clears the PCI bus target abort interrupt. 1: Cleared MSK_SERR R/W Sets the mask status of the PCI bus system error (SERR# reception) interrupt. 0: Not masked 1: Masked MSK_PERR R/W Sets the mask status of the PCI bus parity error (PERR# reception) interrupt. 0: Not masked 1: Masked MSK_MAB R/W Sets the mask status of the PCI bus master abort interrupt. 0: Not masked 1: Masked MSK_TAB R/W Sets the mask status of the PCI bus target abort interrupt. 0: Not masked 1: Masked SERR R Detects the occurrence status of a PCI bus system error (SERR# reception). 1: System error occurred PERR R Detects the occurrence status of the PCI bus parity error (PERR# reception). 1: Parity error occurred MABORT R Detects the occurrence status of the PCI bus master abort. 1: Master abort occurred TABORT R Detects the occurrence status of the PCI bus target abort. 1: Target abort occurred PERR Application Note U17121EJ1V1AN 39 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.7 PCI_ERR_ADD register The PCI_ERR_ADD register retains the PCI bus address when the following errors occur. * System error (SERR# reception) * Parity error (PERR# reception) * Master abort * Target abort When the PCI_ERR_ADD register is read, all the bits are cleared. Once an error occurs and a value is set to the PCI_ERR_ADD register, the first value is retained until read access is performed or a new error occurs and the value is updated. This function is used only for debugging and is not used in normal operation. After reset: 00000000H 31 ERR_ADR R Offset address: 1CH 0 Bit Name ERR_ADR R/W R Function Retains the address when a PCI bus error occurs. 40 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.8 SYSTEM_MEM_BASE register When the main memory is accessed from the PCI device by setting the SYSTEM_MEM_BASE register and SYSTEM_MEM_RANGE register, the register responds to an access of a matching address. After reset: 00000000H 31 S_BASE R/W Offset address: 40H 16 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name S_BASE R/W R/W Function Sets the higher 16 bits (bits 16 to 31) of the base address on the PCI bus memory space in which the main memory (SDRAM) is mapped. 3.4.9 SYSTEM_MEM_RANGE register After reset: 0000FFFFH 31 S_RANGE R/W Offset address: 44H 16 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 Bit Name S_RANGE R/W R/W Function Sets the range of the PCI bus memory space in which the main memory (SDRAM) is mapped. It can be set in 64 KB units. 0000H: 64 KB 0001H: 128 KB : 000FH: 1 MB : 00FFH: 16 MB : 0FFFH: 256 MB : FFFFH: 4 GB Application Note U17121EJ1V1AN 41 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.4.10 SDRAM_CTL register After reset: 00070230H 31 R/W 24 23 Offset address: 48H 16 15 13 12 11 10 BUS_SIZE 9 8 CAS_LATENCY 7 6 5 4 WAIT_STATE 3 2 1 0 COLUMN_SIZE 0 0 0 0 0 0 0 0 CYCLE_LATENCY 0 0 0 0 0 0 0 0 0 Bit Name CYCLE_LATENCY R/W R/W Function Sets the latency for successive main memory (SDRAM) accesses from the PCI device. A latency of up to 7,650 ns can be set. 00H: No latency 01H: 1 PCI clock (30 ns) : FFH: 255 PCI clocks (7,650 ns) BUS_SIZE R/W Sets the bit width of the data bus. 0: 16-bit width 1: 32-bit width CAS_LATENCY R/W Sets the CAS latency. 00: Setting prohibited 01: 1 10: 2 11: 3 Sets the wait interval of ACT CMD, PRE ACT, and CMD ACT. 00: Setting prohibited 01: 1 clock 10: 2 clocks 11: 3 clocks WAIT_STATE R/W COLUMN_SIZE R/W Sets the bit width of the column address. 00: 8-bit width 01: 9-bit width 10: 10-bit width 11: 11-bit width 42 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO The correspondence between the output address signals when the main memory (SDRAM) is accessed and the PCI bus address signals is shown below. Table 3-1. Row Address Output COLUMN_SIZE Field Setting Value 25 to 18 00 (8 bits) 01 (9 bits) 10 (10 bits) 11 (11 bits) 25 to 18 25 to 18 25 to 18 25 to 18 17 25 17 17 17 16 24 25 16 16 15 23 24 25 15 14 22 23 24 25 Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins (O_SD_ADR1 to O_SD_ADR25) 13 21 22 23 24 12 20 21 22 23 11 19 20 21 22 10 18 19 20 21 9 17 18 19 20 8 16 17 18 19 7 15 16 17 18 6 14 15 16 17 5 13 14 15 16 4 12 13 14 15 3 11 12 13 14 2 10 11 12 13 1 9 10 11 12 Table 3-2. Column Address Output (Precharge Command) BUS_SIZE Bit Setting Value 25 to 18 0 (16 bits) 1 (32 bits) 25 to 18 25 to 18 17 17 17 16 16 16 15 15 15 14 14 14 Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins (O_SD_ADR1 to O_SD_ADR25) 13 12 12 12 11 H 11 H 11 10 10 10 9 9 9 8 8 8 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 Remark H: High level Table 3-3. Column Address Output (Read/Write Command) BUS_SIZE Bit Setting Value Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins (O_SD_ADR1 to O_SD_ADR25) 25 to 18 17 17 17 16 16 16 15 15 15 14 14 14 13 12 12 12 11 L 11 L 11 10 10 10 9 9 9 8 8 8 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 (16 bits) 1 (32 bits) 25 to 18 25 to 18 Remark L: Low level Application Note U17121EJ1V1AN 43 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.5 Address Map The address maps of the CPU memory space and PCI bus I/O or memory space are shown below. Figure 3-3. CPU Memory Space/PCI Bus I/O Space Address Map CPU memory space PCI bus I/O space FFFF FFFFH FFFFH I_CPU_CS1_B area 0000H PCI I/O area 64 KB PCI bus I/O space 64 KB IO_BASE[31:16] + FFFFH IO_BASE[31:16] + 0000H 0000 0000H Figure 3-4. CPU Memory Space/PCI Bus Memory Space Address Map CPU memory space PCI bus memory space FFFF FFFFH FFFFFH I_CPU_CS2_B area 00000H PCI memory area 1 MB PCI memory space 1 MB M_BASE[31:16] + FFFFFH M_BASE[31:16] + 00000H S_BASE[31:16] + S_RANGE[31:16] + FFFFH O_SD_CS_B output when accessing from PCI host bridge Main memory (SDRAM) area Main memory space S_BASE[31:16] + S_RANGE[31:16] + 0000H 0000 0000H 44 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.6 Initializing PCI Host Bridge Macro The PCI host bridge macro must be initialized according to the following procedure to acknowledge memory access and I/O access to the PCI bus and main memory (SDRAM) access from the PCI device. Figure 3-5. Initializing PCI Host Bridge Macro Internal PCI bus reset released PCI_CONTROL register Set PCI_RESET bit to 1 PCI I/O area setting PCI memory area setting PCI_MEM_BASE register Set any address to M_BASE field PCI_I/O_BASE register Set any address to I/O_BASE field PCI_CONTROL register Set MEM_EN and IO_EN bits to 11 Main memory (SDRAM) area setting SYSTEM_MEM_BASE register Set any address to S_BASE field SYSTEM_MEM_RANGE register Set any value to S_RANGE field SDRAM control setting SDRAM_CTL register Set bit width of column address to COLUMN_SIZE field Set number of wait clocks to WAIT_STATE field Set CAS latency to CAS_LATENCY field Set BUS_SIZE bit to bit width of data bus Set latency between successive accesses to CYCLE_LATENCY field PCI bus control setting PCI_CONTROL register Set TARGET_EN bit to 1 Set required bit of PCI_REQ field to 1 Application Note U17121EJ1V1AN 45 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.7 Bus Width of External Bus Interface The operation mode of the data bus with respect to the external bus interface can be changed via the I_MODE16 pin status. Cautions 1. Do not change the status of the I_MODE16 pin during operation. 2. The I_MODE16 pin can only be used to change the operation mode of the data bus with respect to the external bus slave interface. To change the data bus width of the SDRAM bus interface, use the BUS_SIZE bit in 3.4.10 SDRAM_CTL register. 3. The setting of the I_MODE16 pin should correspond with the external bus interface operation mode of the CPU. 4. When 16-bit mode is set, the access cycle is divided for 32-bit access on the external bus interface. Accordingly, access is divided similarly on the PCI bus interface. Therefore, when 16-bit mode is set, because a 32-bit access cycle is not generated on the PCI bus interface, a PCI device whose registers are only valid for 32-bit access cannot be accessed. Table 3-4. I_MODE16 Pin Status and Operation Mode of Data Bus I_MODE16 Pin Low level High level Data Bus Operation Mode 32-bit mode 16-bit mode Remark 32-bit data bus 16-bit data bus 46 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.8 Timing The timing for each interface of the PCI host bridge macro is shown below. 3.8.1 External bus interface timing CPU write/CPU read access is performed from the CPU using the bus interface (Figures 3-6 and 3-7). When accessing SDRAM from the PCI host bridge macro, bus hold is performed and the main memory is write/read accessed (Figures 3-8 to 3-10). Figure 3-6. CPU Write Access I_PCLK I_CPU_CSx_B I_CPU_ADR0 to I_CPU_ADR19 I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_WE_B I_CPU_WAIT_B I_CPU_DATA0 to I_CPU_DATA31 Valid 1111 Valid 0000 1111 Remark x = 0 to 2 Figure 3-7. CPU Read Access I_PCLK I_CPU_CSx_B I_CPU_ADR0 to I_CPU_ADR19 I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_OE_B I_CPU_WAIT_B I_CPU_DATA0 to I_CPU_DATA31 EN_CPU_DATA Valid 1111 Valid 0000 1111 Remark x = 0 to 2 Application Note U17121EJ1V1AN 47 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO Figure 3-8. Hold Request/Hold Acknowledge I_SDCLK O_HOLDREQ_B I_HOLDACK_B EN_SD_CTL SDRAM control signal output Figure 3-9. Main Memory (SDRAM) Write Access (8-Burst) I_SDCLK O_HOLDREQ_B I_HOLDACK_B O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B O_SD_ADR1 to O_SD_ADR25 O_SD_DATA0 to O_SD_DATA31 O_SD_DQM_B0 to O_SD_DQM_B3 1111 RA CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 WD0 WD1 WD2 WD3 WD4 WD5 WD6 WD7 1111 Remark SDRAM_CTL register WAIT_STATE field = 10, CAS_LATENCY field = 10 48 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO Figure 3-10. Main Memory (SDRAM) Read Access (8-Burst) I_SDCLK O_HOLDREQ_B I_HOLDACK_B O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B O_SD_ADR1 to O_SD_ADR25 I_SD_DATA0 to I_SD_DATA31 O_SD_DQM_B0 to O_SD_DQM_B3 1111 RA CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 0000 1111 Remark SDRAM_CTL register WAIT_STATE field = 10, CAS_LATENCY field = 10 Application Note U17121EJ1V1AN 49 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO 3.8.2 PCI bus interface timing The PCI host bridge macro supports the following PCI bus interface timing. (1) PCI bus master cycle timing The timing of access from the CPU to the PCI device is shown below. (a) Configuration read/write cycle, I/O read/write cycle, and memory read/write cycle (i) Read cycle Timing type: Configuration register read, internal I/O register read, memory read Figure 3-11. Read Cycle PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# H (ii) Write cycle Timing type: Configuration register write, internal I/O register write, memory write Figure 3-12. Write Cycle PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# H 50 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (b) Target abort cycle Timing type: Target abort Figure 3-13. Target Abort Cycle PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# H (c) Master abort cycle Timing type: Master abort cycle Figure 3-14. Master Abort Cycle PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# PAR H H H Application Note U17121EJ1V1AN 51 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (d) Data parity error Timing type: Single read & write cycle data parity error Figure 3-15. Data Parity Error PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# H (2) PCI bus slave cycle timing The timing of access from the PCI device to SDRAM is shown below. (a) Memory single read cycle Timing type: Memory single read cycle Figure 3-16. Single Read Cycle PCICLK REQ# GNT# AD FRAME# IRDY# DEVSEL# TRDY# STOP# 52 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (b) Memory single write cycle Timing type: Memory single write cycle Figure 3-17. Single Write Cycle PCICLK REQ# GNT# AD FRAME# IRDY# DEVSEL# TRDY# STOP# (c) Burst read cycle Timing type: Memory burst read cycle - Not disconnect Figure 3-18. Burst Read Cycle PCICLK REQ# GNT# AD FRAME# IRDY# DEVSEL# TRDY# H 0 1 2 3 4 5 6 7 STOP# Application Note U17121EJ1V1AN 53 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (d) Burst write cycle Timing type: Memory burst write cycle - Not disconnect Figure 3-19. Burst Write Cycle PCICLK REQ# GNT# AD FRAME# IRDY# DEVSEL# TRDY# H 0 1 2 3 4 5 6 7 STOP# (e) Abort cycle Timing type: Target abort cycle & master abort cycle Figure 3-20. Abort Cycle PCICLK REQ# GNT# AD FRAME# IRDY# DEVSEL# TRDY# STOP# SERR# H 54 Application Note U17121EJ1V1AN CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (f) Data parity error (i) Read data parity error 1 Timing type: Single read cycle data parity error Figure 3-21. Read Data Parity Error PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# H (ii) Read data parity error 2 Timing type: Burst read cycle data parity error Figure 3-22. Read Data Parity Error 2 PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# Application Note U17121EJ1V1AN 55 CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO (iii) Write data parity error 1 Timing type: Single write cycle data parity error Figure 3-23. Write Data Parity Error 1 PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# SERR# H (iv) Write data parity error 2 Timing type: Burst write cycle data parity error Figure 3-24. Write Data Parity Error 2 PCICLK AD FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# SERR# 56 Application Note U17121EJ1V1AN CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION This chapter describes configuration examples in which the PCI host bridge macro is integrated in an FPGA (Altera's EP20K200EQC240-1X). 4.1 Conditions for Configuration Examples of FPGA Integration The conditions in the configuration examples are as follows. (1) CPU: (3) CS space of PCI host bridge: (4) CS space of SDRAM: (5) SDRAM: (6) PCI connection: V850E/ME2 CSZ6 CSZ3 Connecting two 16 M x 16 SDRAMs (4 M x 16 x 4 banks) 2 devices (2) Bus width of external bus interface: 32 bits 4.2 Points to Remember When Creating Top Layer of FPGA Points to remember when integrating the PCI host bridge macro with an FPGA are indicated below. (1) First decode the chip select from the address before creation. * I_CPU_CS0_B: PCI host bridge register chip select (Offset address in 3.4 Registers) * I_CPU_CS1_B: PCI I/O area chip select (See Figure 3-3 CPU Memory Space/PCI Bus I/O Space Address Map) * I_CPU_CS2_B: PCI memory area chip select (See Figure 3-4 CPU Memory Space/PCI Bus Memory Space Address Map) (2) Because the buffers of the address bus and data bus for the expansion bus interface are output when the PCI host bridge controls SDRAM, they become bidirectional pins via the selector. The following pins that control SDRAM become 3-state output. * DQM0 to DQM3, SDCKE, SDCS, SDRAS, SDCAS, SDWEZ (3) The following PCI bus interface pins become bidirectional pins. * AD, CBE, FRAME, IRDY, DEVSEL, TRDY, STOP, PAR, PERR (4) There are three interrupt request output signals: one is output from the PCI host bridge; the remaining two are INTA and INTB signals from the external PCI slot and are directly connected to the CPU. Application Note U17121EJ1V1AN 57 CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.3 Reference Diagram for FPGA Top Connection The reference diagram for connecting the PCI host bridge macro with the FPGA top layer is shown below. FPGA top PCI host bridge macro VBRESETZ CSZ6 RA21 to RA25 RA0 Address decoder I_SRST_B I_CPU_CS0_B I_CPU_CS1_B I_CPU_CS2_B I_CPU_ADR0 I_CPU_ADR1 to I_CPU_ADR19 RA1 to RA25 O_SD_ADR1 to O_SD_ADR25 I_PCLK O_PCIRST_B I_AD0 to I_AD31 O_AD0 to O_AD31 EN_AD I_CBE0 to I_CBE3 O_CBE0 to O_CBE3 EN_CBE I_CPU_DATA0 to I_CPU_DATA31 I_SD_DATA0 to I_SD_DATA31 RD0 to RD31 Selector O_CPU_DATA0 to O_CPU_DATA31 O_SD_DATA0 to O_SD_DATA31 EN_CPU_DATA EN_SD_DATA0, EN_SD_DATA1 BENZ0 to BENZ3 WRZ0 RDZ WAITZ HLDRQZ HLDAKZ SDCLK DQM0 to DQM3 SDCKE SDCS SDRASZ SDCASZ SDWEZ I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_WE_B I_CPU_OE_B O_CPU_WAIT_B O_HOLDREQ_B I_HOLDACK_B I_SDCLK O_SD_DQM_B0 to O_SD_DQM_B3 O_SD_CKE O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B EN_SD_CTL Open EN_SDCLK I_FRAME_B O_FRAME_B EN_FRAME I_IRDY_B O_IRDY_B EN_IRDY I_DEVSEL_B O_DEVSEL_B EN_DEVSEL I_TRDY_B O_TRDY_B EN_TRDY I_STOP_B O_STOP_B EN_STOP I_PAR O_PAR EN_PAR I_PERR_B O_PERR_B EN_PERR I_SERR_B I_REQ_B1 I_REQ_B2 I_REQ_B3 to I_REQ_B7 O_GNT_B1 O_GNT_B2 O_GNT_B3 to O_GNT_B7 O_PCIHOST_IN INT0 INT1 INT2 INTA INTB Open Internal H fixed input GNT1 GNT2 SERR REQ1 REQ2 PERR PAR STOP TRDY DEVSEL IRDY FRAME CBE0 to CBE3 AD0 to AD31 PCLK PCIRST 58 Application Note U17121EJ1V1AN CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.4 FPGA Top Pin Functions The pin information when integrating the PCI host bridge macro with an FPGA is shown below. 4.4.1 CPU bus slave interface pins Pin Name VBRESETZ CSZ6 RA0 to RA25 RD0 to RD31 BENZ0 to BENZ3 WRZ RDZ WAITZ INT0 I/O Input Input I/O I/O Input Input Input Output Output System reset input PCI host bridge chip select input CPU address I/O CPU data I/O CPU data byte enable input CPU data write enable input CPU data read enable input CPU data wait output PCI host bridge interrupt output Function 4.4.2 SDRAM bus interface pins Pin Name HLDREQZ HLDACKZ SDCLK SDCKE SDCS SDRASZ SDCASZ SDWEZ DQM0 to DQM3 I/O Output Input Input Output Output Output Output Output Output Function SDRAM bus hold request output SDRAM bus hold acknowledge input SDRAM clock input SDRAM clock enable output SDRAM chip select output SDRAM row address strobe output SDRAM column address strobe output SDRAM read/write output SDRAM output disable output Application Note U17121EJ1V1AN 59 CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.4.3 PCI bus interface pins Pin Name PCLK PCIRST AD0 to AD31 CBE0 to CBE3 FRAME IRDY DEVSEL TRDY STOP PAR PERR SERR REQ1, REQ2 GNT1, GNT2 INT1, INT2 I/O Input Output I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Output Output PCI clock input PCI reset output PCI address/data I/O PCI command/byte enable I/O PCI frame I/O PCI initiator ready I/O PCI device select I/O PCI target ready I/O PCI stop I/O PCI parity I/O PCI parity error I/O PCI system error input PCI request input PCI grant output PCI INTA, INTB output Function 60 Application Note U17121EJ1V1AN CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5 FPGA Top Pin Configuration The connection diagram of the PCI host bridge macro pins in an FPGA is shown below. 4.5.1 Internal connection diagram of external bus interface FPGA top PCI host bridge macro I_SRST_B I_CPU_CS0_B I_CPU_CS1_B I_CPU_CS2_B I_SRST_B I_CPU_ADR1 to I_CPU_ADR19 O_SD_ADR1 to O_SD_ADR25 I_CPU_DATA0 to I_CPU_DATA31 I_SD_DATA0 to I_SD_DATA31 O_CPU_DATA0 to O_CPU_DATA31 O_SD_DATA0 to O_SD_DATA31 EN_CPU_DATA EN_SD_DATA0, EN_SD_DATA1 I_CPU_BE_B0 to I_CPU_BE_B3 O_SD_DQM_B0 to O_SD_DQM_B3 I_CPU_WE_B O_SD_WR_B I_CPU_OE_B O_CPU_WAIT_B O_PCIHOST_INT O_HOLDRQ_B I_HOLDACK_B O_SD_CKE O_SD_CS_B O_SD_RAS_B O_SD_CAS_B I_SDCLK EN_SD_CTL I/O buffer WRZ RDZ WAITZ INT0 HLDRQZ HLDAKZ SDCKE SDCSZ SDRASZ SDCASZ SDCLK WE/WR RD WAIT INTP10 HLDRQ HLDAK SDCKE CS3 SDRAS SDCAS BUSCLK Selector Selector BENZ0 to BENZ3 DQM0 to DQM3 xxBE/xxDQM External bus interface VBRESETZ CS6 Address decoder RA0 RESET CS6 A0 RA1 to RA25 A1 to A25 RD0 to RD31 D0 to D31 Application Note U17121EJ1V1AN 61 CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5.2 Internal connection diagram of PCI bus interface FPGA top PCI host bridge macro I_PCLK O_PCIRST_B I_AD0 to I_AD31 O_AD0 to O_AD31 EN_AD I_CBE0 to I_CBE3 O_CBE0 to O_CBE3 EN_CBE I_FRAME_B O_FRAME_B EN_FRAME I_IRDY_B O_IRDY_B EN_IRDY I_DEVSEL_B O_DEVSEL_B EN_DEVSEL I_TRDY_B O_TRDY_B EN_TRDY I_STOP_B O_STOP_B EN_STOP I_PAR O_PAR EN_PAR I_PERR_B O_PERR_B EN_PERR I_SERR_B SERR SERR# PERR PERR# PAR PAR STOP STOP# TRDY TRDY# PCI bus DEVSEL DEVSEL# IRDY IRDY# FRAME FRAME# CBE0 to CBE3 C/BE0# to C/BE3# AD0 to AD31 AD0 to AD31 PCLK PCIRST CLK RST# I_REQ_B1, I_REQ_B2 I_REQ_B3 to I_REQ_B7 O_GNT_B1, O_GNT_B2 O_GNT_B3 to O_GNT_B7 Open I/O buffer H fixed REQ1, REQ2 REQ1#, REQ2# GNT1, GNT2 GNT1#, GNT2# 62 Application Note U17121EJ1V1AN CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5.3 External connection diagram of external bus interface (example of connection with V850E/ME2) System reset FPGA (PCI host bridge) VBRESETZ RA2 to RA14 RA24, RA25 RD0 to RD31 BENZ0 to BENZ3 WRZ SDCKE SDCS SDRASZ SDCASZ SDCLK RDZ WAITZ INT0 HLDRQZ HLDAKZ V850E/ME2 RESET HLDAK HLDRQ INTPxxx WAIT RD A0 to A22 A24, A25 D0 to D31 xxBE/xxDQM WR/WE SDCKE CSx SDRAS SDCAS BUSCLK SDRAM1 A0 to A12 BA0, BA1 DQ0 to DQ31 DQM0, DQM1 /WE CKE /CS /RAS /CAS CLK DQM2, DQM3 SDRAM2 Remarks 1. This is an example using two SDRAMs of 4 M words x 16 bits x 4 banks (row address: 13 bits, column address: 9 bits). 2. xx: LL, LU, UL, UU Application Note U17121EJ1V1AN 63 CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.5.4 External connection diagram of PCI bus interface PCI bus clock PCI host bridge PCLK AD00 to AD31 CBE0 to CBE3 PCIRST FRAME IRDY DEVSEL TRDY STOP PAR PERR SERR REQ1 GNT1 PCI device 1 AD00 to AD31 IDSELNote C/BE0# to C/BE3# RST# FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# SERR# REQ# GNT# PCI device AD00 to AD31 IDSELNote C/BE0# to C/BE3# RST# FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# SERR# CLK CLK REQ2 GNT2 REQ# GNT# Note Connect one of the AD31 to AD11 signals to the IDSEL pin of each PCI device. 64 Application Note U17121EJ1V1AN CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION 4.6 Cautions on Designing FPGA Cautions when fitting an FPGA using Altera's "Quartusll Design Software" are shown below. 4.6.1 FPGA fitting design (1) Set the "I/O Standard" buffer type to "3.3-V PCI" for the following PCI bus interface pins. Pin Name/Usage INTA INTB FRAME DEVSEL REQ1 REQ2 GNT1 GNT2 IRDY TRDY STOP PCIRST AD0 to AD31 CBE0 to CBE3 PAR PERR SERR input input bidir bidir input input output output bidir bidir bidir output bidir bidir bidir bidir input Dir I/O Standard 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI 3.3-V PCI (2) Determine the pin assignment taking equal length wiring into consideration for the PCI bus interface pins. (3) Specify the "PCLK" and "SDCLK" signals as Global CLK. 4.6.2 PCI bus interface timing parameters (as constraint of PCI CLK = 33 MHz) Adjust the timing so that the following PCI specification values are satisfied. (1) Input setup time to CLK point to point Pin REQ1, REQ2 Other PCI pins 10 ns 7 ns Setup 0 ns 0 ns Hold Application Note U17121EJ1V1AN 65 CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION (2) CLK to signal valid delay signals Pin All PCI pins 2 ns MIN. 11 ns MAX. The following specification values apply to the PCI bus timing (PCI CLK = 33 MHz). Figure 4-1. Output Timing CLK TVAL Output delay Figure 4-2. Input Timing CLK TSU Input TH Inputs valid Table 4-1. 33 MHz Timing Parameters Symbol TVAL TVAL (ptp) TSU TSU (ptp) TH Parameter CLK to signal valid delay bused signals CLK to signal valid delay point to point signals Input setup time to CLK bused signals Input setup time to CLK point to point signals Input hold time from CLK MIN. (ns) 2 2 7 10 0 MAX. (ns) 11 12 4.6.3 SDRAM interface timing The timing for interfacing with SDRAM depends on the external bus interface and the SDRAM to be connected. Adjust the timing to suit the system. 66 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES This chapter introduces the configuration of an evaluation board that mounts the V850E/ME2, as well as program examples. This is an example of an application used to operate a HDD with an IDE controller mounted on the PCI connecter. 5.1 Block Diagram of Evaluation Board A block diagram of the evaluation board is shown below. Figure 5-1. Block Diagram of Evaluation Board N-Wire connector PCI host evaluation board MEMC bus SDRAM (64 MB) SRAM (1 MB) MEMC bus PCI connector PCI connector PCI bus PCI-IDE controller Hard disk drive V850E/ME2 (176-pin LQFP) PCI host bridge macro Flash memory 7-segment/ SW ROM socket (for emulation) PCI bus Application Note U17121EJ1V1AN 67 CHAPTER 5 APPLICATION EXAMPLES 5.2 Specifications of Evaluation Board The specifications of the evaluation board are as follows. Table 5-1. Specifications of Evaluation Board Item CPU CPU operating frequency MEMC bus operating frequency Evaluation board memory Flash memory SRAM SDRAM Evaluation board peripheral I/O PCI host bridge Other 7-segment display 7-segment display x 2 can be controlled by V850E/ME2 general-purpose port CSZ6 area (32-bit width): PCI Rev.2.1 compliant host interface (33 MHz) CSZ0 area (32-bit width): 8 MB CSZ1 area (32-bit width): 1 MB CSZ3 area (32-bit width): 64 MB V850E/ME2 30 MHz 30 MHz Description The device numbers of the PCI bus are assigned as follows. Table 5-2. IDSEL Connection Slot PCI Slot 1 (J2) PCI Slot 2 (J3) Device Number AD31 AD30 Remark Connect AD31 to IDSEL Connect AD30 to IDSEL 68 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES 5.3 Example of Evaluation Board Connection Circuit A circuit example of connection of the V850E/ME2 with SDRAM, FPGA, and a PCI device (slot) is shown below. Figure 5-2. Example of Evaluation Board Connection Circuit System reset PCI bus clock V850E/ME2 RESET CS6 CS3 A0 to A25 RD xxBE xxWR RD WAIT INT0 INT1 INT2 HLDRQ HLDAK BUSCLK SDCKE SDRAS SDCAS WE FPGA (PCI host bridge) VBESTZ CSZ6 PCLK PCIRST AD0 to AD31 PCI device CLK RST# AD0 to AD31 IDSEL# C/BE#0 to C/BE#3 FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# SERR# REQ# GNT# INT# PCI device CLK RST# AD0 to AD31 IDSEL# C/BE#0 to C/BE#3 FRAME# IRDY# DEVSEL# TRDY# STOP# PAR PERR# SERR# REQ# GNT# INT# RA0 to RA25 RD0 to RD25 CBE0 to CBE3 FRAME BENZ0 to BENZ3 IRDY WRZ0 to WRZ3 DEVSEL RDZ TRDY WAITZ STOP INT0 PAR INT1 PERR INT2 SERR HLDRQZ REQ1 HLDAKZ GNT1 DQM0 to DQM3 INTA SDCLK SDCKE SDCS SDRASZ SDCASZ SDWEZ SDRAM SDRAM A0 to A12 A2 to A14 BA0, BA12 A24, A25 D0 to D31 DQM2, DQM0, DQM1 DQM3 CLK CKE CS RAS CAS WE REQ2 GNT2 INTB Remark xx: LL, LU, UL, UU Application Note U17121EJ1V1AN 69 CHAPTER 5 APPLICATION EXAMPLES 5.4 Evaluation Board Memory Space The evaluation board memory space is shown below. Figure 5-3. Evaluation Board Memory Space FFF FFFFH On-chip peripheral I/O area (4 KB) FFF F000H FFF EFFFH On-chip data RAM area (16 KB) FFF B000H FFF AFFFH Access-prohibited area FFF 8000H FFF 7FFFH Area 3 (64 MB) PCI host bridge CS area (63.9 MB) CSZ6 PCI host bridge area (8 MB) CFF FFFFH C80 0000H C00 0000H BFF FFFFH Area 2 (64 MB) Reserved area (area 2 = 64 MB) 256 MB 800 0000H 7FF FFFFH 7FF FFFFH Area 1 (64 MB) SDRAM area (area 1 = 64 MB) CSZ3 External SRAM area (64 MB) 400 0000H 3FF FFFFH On-chip peripheral I/O mirror (4 KB) 3FF F000H 3FF EFFFH On-chip data RAM mirror (16 KB) 3FF B000H 3FF AFFFH Access-prohibited area 3FF 8000H 3FF 7FFFH 400 0000H Area 0 (64 MB) 080 0000H 07F FFFFH SRAM area (56 MB) 08F FFFFH CSZ1 External SRAM area (1 MB) 080 0000H 07F FFFFH Flash memory area (7 MB) CSZ0 ROM area (7 MB) 010 0000H 00F FFFFH 000 0000H On-chip instruction RAM area (1 MB) 70 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES The PCI memory I/O space is assigned to the CSZ6 area. The base address of the PCI memory space is set to CC0 0000H. The base address of the PCI I/O space is set to C80 0000H. Figure 5-4. Comparison Between CPU Memory Space and PCI Memory Space CPU memory space PCI memory space FFFF FFFFH CFF FFFFH CS6 area (4 MB) CC0 0000H PCI memory area PCI memory area PCI_MEM_BASE[31:22] + 00 0000H PCI_MEM_BASE[31:22] + 3F FFFFH SYSTEM_MEM_BASE SYSTEM_MEM_BASE Main memory area (SDRAM) Main memory area (SDRAM) SYSTEM_MEM_BASE SYSTEM_MEM_BASE 0000 0000H Figure 5-5. Comparison Between CPU Memory Space and PCI I/O Space CPU memory space PCI I/O space FFFF FFFFH CBF FFFFH PCI bridge I/O area CA0 0000H CS6 area (4 MB) C80 0000H PCI I/O area PCI I/O area (2 MB) PCI_MEM_BASE[31:21] + 1F FFFFH PCI_MEM_BASE[31:21] + 00 0000H 0000 0000H Application Note U17121EJ1V1AN 71 CHAPTER 5 APPLICATION EXAMPLES 5.5 Sample Program Examples This sample program is assumed to be used in an environment with the PCI-IDE board connected to the V850E/ME2 evaluation board as the PCI device. The PCI-IDE board is connected to the IDE HDD, and the sample program accesses the IDE HDD. 5.5.1 Development tools (1) MULTI TM 1.8.9 TM Integrated development environment made by Green Hills Software , Inc. (2) PCI-IDE board IDE card of PCI interface connected to evaluation board. Used by connecting IDE HDD in this application. 5.5.2 Program configuration The sample program configuration is shown below. (1) PCI host bridge macro initialization sample program list First the PCI host bridge macro must be initialized for the CPU to access the PCI area. The correspondence between the PCI memory space and CPU memory space, the interrupts from PCI, and access control from the CPU to the PCI memory space are set by the PCI host bridge macro registers. (2) PCI configuration space access sample program list When initialization of the PCI host bridge macro ends, initialization of each PCI device connected to the PCI bus is performed. Initialization is performed mainly by setting the configuration space registers existing in each PCI device. The configuration space registers can be accessed only by executing a configuration cycle using the PCI_CONFIG_ADD and PCI_CONFIG_DATA registers described in the register descriptions. (3) IDE HDD access sample program list When initialization of the PCI host bridge macro and PCI devices ends, the PCI device can actually be operated. The PCI device is operated by setting the registers assigned to the configuration space and PCI I/O area. The IDE bus setting is performed and the IDE HDD is actually accessed by operating the PCI-IDE board registers in this sample code. 72 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES 5.5.3 V850E/ME2 PCI host bridge macro initialization sample program list ///////////////////////////////////////////////////////////////// // // // // // // // // // // PCI_HBM_Init() is called after functions required for accessing Host Bridge Macro, such as CPU and peripheral I/O, are initialized. V850E/ME2 - PCI Host Bridge Macro initialization sample Overview: Initializes PCI Host Bridge Macro by setting PCI Bridge IO area register group. Specific initialization is described in function PCI_HBM_Init(). // // // // // // // // // // ///////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////// // // // Defines base address of PCI area and SDRAM area. of SDRAM area is 0400_0000H in this application. (0x0C800000) (BASE_ADDRESS_ME2PCIIF) (BASE_ADDRESS_ME2PCIIF + 0x00200000) (BASE_ADDRESS_ME2PCIIF + 0x00400000) (0x04000000) (0x03FFFFFF) // 64MB // // Start address of PCI area is 0C80_0000H, and start address // ///////////////////////////////////////////////////////////////// #define BASE_ADDRESS_ME2PCIIF #define BASE_ADDRESS_PCI_IO #define BASE_ADDRESS_PCI_BRIDGE_IO #define BASE_ADDRESS_PCI_MEM #define BASE_ADDRESS_SDRAM #define RANGE_SDRAM //////////////////////////////////////////////////////// // PCI Host Bridge Macro register address definition // (BASE_ADDRESS_PCI_BRIDGE_IO+0x00) (BASE_ADDRESS_PCI_BRIDGE_IO+0x04) (BASE_ADDRESS_PCI_BRIDGE_IO+0x08) (BASE_ADDRESS_PCI_BRIDGE_IO+0x10) (BASE_ADDRESS_PCI_BRIDGE_IO+0x14) (BASE_ADDRESS_PCI_BRIDGE_IO+0x18) (BASE_ADDRESS_PCI_BRIDGE_IO+0x1C) (BASE_ADDRESS_PCI_BRIDGE_IO+0x40) (BASE_ADDRESS_PCI_BRIDGE_IO+0x44) (BASE_ADDRESS_PCI_BRIDGE_IO+0x48) //////////////////////////////////////////////////////// #define PHBMR_PCI_CONFIG_DATA #define PHBMR_PCI_CONFIG_ADD #define PHBMR_PCI_CONTROL #define PHBMR_PCI_IO_BASE #define PHBMR_PCI_MEM_BASE #define PHBMR_PCI_INT_CTL #define PHBMR_PCI_ERR_ADD #define PHBMR_SYSTEM_MEM_BASE #define PHBMR_SYSTEM_MEM_RANGE #define PHBMR_SDRAM_CTL /////////////////////////////////////////// // Macro definition for register access // *((volatile unsigned int *)((int)x)) /////////////////////////////////////////// #define V850EME2_REGW(x) Application Note U17121EJ1V1AN 73 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////// // Function name: PCI_HBM_Init // Function: Initializes PCI Host Bridge Macro. // Argument: None // Return value: None // // // // // // // // - Base address of PCI I/O space: 0C80_0000H // // // // // // // // // // // // // Remark: Base addresses of this initialization sample are as follows.// - Base address of PCI memory space: 0CC0_0000H - Base address on PCI bus memory space in which main memory (SDRAM) is mapped: main memory (SDRAM) is mapped: requirements and mounting. 0400_0000H 03FF_FFFFH - Range of PCI bus memory space in which Other settings are required according to system ///////////////////////////////////////////////////////////////////////// void PCI_HBM_Init(void) { V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000110; // PCI_CONTROL register // // // // bit 15-08: bit 4: bit 31-24: PCI_PARKCNT = 1 (Set time for shifting to bus parking to 7) PCI_REQ = 1 (Enable I_REQ_B0) PCI_RESET bit = 1 (Release PCI bus reset) V850EME2_REGW(PHBMR_PCI_IO_BASE) = BASE_ADDRESS_PCI_IO; // PCI_IO_BASE register // Set PCI I/O space base address to C800000H. V850EME2_REGW(PHBMR_PCI_MEM_BASE) = BASE_ADDRESS_PCI_MEM; // PCI_MEM_BASE register // Set PCI memory space base address to CC00000H. V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000113; // PCI_CONTROL register // // // // // // // // bit 0: bit 15-08: bit bit 4: 1: bit 31-24: PCI_PARKCNT = 1 (Set time for shifting to bus parking to 7) PCI_REQ = 1 PCI_RESET bit = 1 PCI_MEM_EN bit = 1 (Enable access from CPU to PCI memory area) PCI_IO_EN bit = 1 (Enable access from CPU to PCI I/O area) (Enable I_REQ_B0) (Release PCI bus reset) V850EME2_REGW(PHBMR_SYSTEM_MEM_BASE) = BASE_ADDRESS_SDRAM; // SYSTEM_MEM_BASE register // // Set base address on PCI bus memory space in which main memory (SDRAM) is mapped to 4000000H. Application Note U17121EJ1V1AN 74 CHAPTER 5 APPLICATION EXAMPLES V850EME2_REGW(PHBMR_SYSTEM_MEM_RANGE) = RANGE_SDRAM; // SYSTEM_MEM_RANGE register // // Set range of PCI bus memory space in which main memory (SDRAM) is mapped to 3FFFFFFH (64 MB). V850EME2_REGW(PHBMR_SDRAM_CTL) = 0x00071211; // SDRAM_CTL register // // // // // // // // // // // bit 01-00: bit 09-08: bit 05-04: bit 12: bit 23-16: CYCLE_LATENCY = 07H (Set latency for successive main memory (SDRAM) access from PCI device to 210 ns) BUS_SIZE = 1B (Set bit width of data bus to 32 bits) CAS_LATENCY = 10B (Set CAS latency to 2) WAIT_STATE = 01B (Set wait interval of ACT CMD, PRE ACT, and CMD ACT to 1 clock) COLUMN_SIZE = 01B (Set bit width of column address to 9 bits) V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000717; // // // // // // // // return; } ///////////////////////////////////////////////////////////////// // Function name: main // Function: Initializes PCI Host Bridge Macro. // Argument: None // Return value: 0: Normal end int main(void) { // Initializes PCI Host Bridge Macro. PCI_HBM_Init(); return 0; } // // // // bit 0: bit 15-08: bit bit 4: 1: bit 31-24: PCI_PARKCNT = 1 (Set time for shifting to bus parking to 7) PCI_REQ = 1 PCI_RESET bit = 1 PCI_MEM_EN bit = 1 (Enable access from CPU to PCI memory area) PCI_IO_EN bit = 1 (Enable access from CPU to PCI I/O area) (Enable I_REQ_B0) (Release PCI bus reset) ///////////////////////////////////////////////////////////////// Application Note U17121EJ1V1AN 75 CHAPTER 5 APPLICATION EXAMPLES 5.5.4 PCI configuration space access sample program list ///////////////////////////////////////////////////////////////////////// // // // // // // // // // // // // // // // // // // // This procedure is combined in functions PCI_ConfigRead and PCI_ConfigWrite shown below. Function PCI_Config_BaseAddressInit uses function PCI_ConfigWrite to set base address register in configuration space. PCI configuration space access sample Overview: Configuration space is accessed using procedure shown below. 1) Write 32-bit value indicating PCI device, function number, and register number to be accessed to PCI_CONFIG_ADD register of PCI Host Bridge Macro. 2) When reading configuration space register, read (word access) 32-bit value in PCI_CONFIG_DATA register of PCI Host Bridge Macro. When writing to configuration space register, write of PCI Host Bridge Macro. // // // // // // // // // // // // // // // // // // (word access) 32-bit value to PCI_CONFIG_DATA register // ///////////////////////////////////////////////////////////////////////// ////////////////////// // Type declaration // ////////////////////// typedef char typedef short int typedef int typedef unsigned char typedef unsigned short int typedef unsigned int typedef volatile unsigned char typedef volatile unsigned short int typedef volatile unsigned int BYTE; HWORD; WORD; UBYTE; UHWORD; UWORD; VUBYTE; VUHWORD; VUWORD; ///////////////////////////////////////////////////////////////// // Function name: PCI_ConfigRead // Function: Reads 32-bit value in PCI configuration space. // Return value: Read configuration space register data UWORD PCI_ConfigRead(UWORD ConfigAdd) { V850EME2_REGW(PHBMR_PCI_CONFIG_ADD) } = ConfigAdd; return V850EME2_REGW(PHBMR_PCI_CONFIG_DATA); // // // // Argument: ConfigAdd: Register address of configuration space// ///////////////////////////////////////////////////////////////// 76 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////// // Function name: PCI_ConfigWrite // Function: Writes 32-bit value to PCI configuration space. // ConfigData: Register data of configuration space // // // // // Argument: ConfigAdd: Register address of configuration space// // Return value: None void PCI_ConfigWrite(UWORD ConfigAdd, UWORD ConfigData) { V850EME2_REGW(PHBMR_PCI_CONFIG_ADD) = ConfigAdd; V850EME2_REGW(PHBMR_PCI_CONFIG_DATA) = ConfigData; return; } ///////////////////////////////////////////////////////////////////////// // Function name: PCI_Config_BaseAddressInit // Function: Sets base address of configuration space. // Argument: None // Return value: None // Details: Sets base address register of offset 10H to 24H in // // // // // // // void PCI_Config_BaseAddressInit(void) { UWORD ConfigAddress; UWORD ConfigData; /////////////////////////////////////// // ATA Command Register Base Address // /////////////////////////////////////// ConfigAddress = 0x40000010; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 4 (000100b), // // -> ATA Command Register Base Address (In the case of PCI-IDE ASIC board used in this application) ATA Command Register Base Address (10H) ATA Control Register Base Address (14H) : : 0C80_0000H 0C80_0008H 0C80_0010H configuration space of PCI device connected to AD30 signal by IDSEL as follows. // // // // // // // // // // // // ///////////////////////////////////////////////////////////////// Bus Master Control Register Base Address(18H) : ///////////////////////////////////////////////////////////////////////// // bit 01-00 : 00b (fixed) PCI_ConfigWrite(ConfigAddress, 0x0C800000); Application Note U17121EJ1V1AN 77 CHAPTER 5 APPLICATION EXAMPLES /////////////////////////////////////// // ATA Control Register Base Address // /////////////////////////////////////// ConfigAddress = 0x40000014; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 5 (000101b), // // -> ATA Control Register Base Address (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) PCI_ConfigWrite(ConfigAddress, 0x0C800008); ////////////////////////////////////////////// // Bus Master Control Register Base Address // ////////////////////////////////////////////// ConfigAddress = 0x40000018; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 6 (000110b) // // -> Bus Master Control Register Base Address (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) PCI_ConfigWrite(ConfigAddress, 0x0C800010); return; } ///////////////////////////////////////////////////////////////// // Function name: main // Function: Sets base address of configuration space. // Argument: None // Return value: 0: Normal end int main(void) { // Initializes PCI Host Bridge Macro. PCI_HBM_Init(); // Sets base address of configuration space. PCI_Config_BaseAddressInit(); return 0; } // // // // ///////////////////////////////////////////////////////////////// 78 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES 5.5.5 IDE HDD access sample program list /////////////////////////////////////////////////////////////////////////////// // // // // // // // // // // // // // // // // // // // // // This sample program is provided with device selection protocol and four transfer protocols as functions. Corresponding transfer protocol function is called from function processing each ATA command. ATA command is executed by executing device selection protocol to determine that command is issued to either Master Device or Slave Device. ATA command is issued Four transfer and data is transferred using transfer protocol corresponding to each ATA command. protocols, PIO datain transfer, PIO dataout transfer, PIO nondata transfer, and DMA transfer, are available. IDLE IMMEDIATE, IDENTIFY DEVICE, SET FEATURE, READ SECTOR(S), WRITE SECTOR(S), READ DMA, WRITE DMA IDE HDD access sample ASIC board connected to PCI slot of evaluation board. ATA commands to be issued are as follows. // // // // // // // // // // // // // // // // // // // // Overview: Issues ATA commands to HDD, which is ATA device, via PCI-IDE // /////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////// // PCI-IDE ASIC board register address definition // ///////////////////////////////////////////////////// ////////////////////// // IDE Command Area // ////////////////////// #define IDEREG_DATA #define IDEREG_ERROR #define IDEREG_ERROR_ERR_BIT #define IDEREG_FEATURES #define IDEREG_SECTOR_COUNT #define IDEREG_SECTOR_NUMBER #define IDEREG_CYLINDER_LOW #define IDEREG_CYLINDER_HIGH #define IDEREG_DEVICE_HEAD #define IDEREG_STATUS #define IDEREG_COMMAND ////////////////////// // IDE Control Area // ////////////////////// Application Note U17121EJ1V1AN ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x00)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x01)) (0x01) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x01)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x02)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x03)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x04)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x05)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x06)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x07)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x07)) 79 CHAPTER 5 APPLICATION EXAMPLES #define IDEREG_ALTERNATE_STATUS #define IDEREG_DEVICE_CONTROL ///////////////////////// // Bus Master I/O Area // ///////////////////////// #define IDEREG_BUSMASTER_START_STOP #define IDEREG_DSCTBL_START_ADDRESS #define IDEREG_INTERRUPT_CONTROL /////////////////////////// // Error code definition // /////////////////////////// #define STATUS_SUCCESS #define STATUS_TIMEOUT_BSY0_DRQ0 #define STATUS_TIMEOUT_DEVICE_SELECTION #define STATUS_TIMEOUT_DRDY1 #define STATUS_TIMEOUT_BSY0 #define STATUS_TIMEOUT_INTRQ #define STATUS_TIMEOUT_BMEND #define STATUS_IDE_ERROR(IDE_ERROR_REG) 0 1 1 2 3 4 5 ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x0E)) ((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x0E)) ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x10)) ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x14)) ((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x18)) (0x10000000 | (UWORD)(IDE_ERROR_REG)) /////////////////////////////////////////////////// // Transfer mode timing setting value definition // /////////////////////////////////////////////////// // See IDE specifications for details of transfer mode timing setting values shown below. // Setting value passed to SET_FEATURES command in Set_Transfer_mode() #define PIO_MODE0 #define UDMA_MODE0 0x08 0x40 // Setting value of timing register (when IDE operation clock is 33 MHz) #define IDE_PIO_TIMING_IDE33MHz_MODE0 #define IDE_UDMA_TIMING1_IDE33MHz_MODE0 #define IDE_UDMA_TIMING2_IDE33MHz_MODE0 //////////////////////////// // Structure declaration // //////////////////////////// /////////////////////////////////////// // Structure for issuing ATA command // /////////////////////////////////////// typedef struct{ UBYTE features; UBYTE sector_count; UBYTE sector_number; // Features register // Sector Count register // Sector Number register Application Note U17121EJ1V1AN (0x00020906) (0x00000202) (0x00000005) 80 CHAPTER 5 APPLICATION EXAMPLES UBYTE cylinder_low; UBYTE cylinder_high; UBYTE device_head; UBYTE command; } ATA_COMMAND; // Cylinder Low register // Cylinder High register // Device/Head register // Command register //////////////////////////////////////////// // Descriptor table for UltraDMA transfer // //////////////////////////////////////////// typedef struct{ UWORD transfer_address; UWORD transfer_byte; UWORD next_table_address; } DISCRIPTOR_TABLE; ///////////////////////////// // Initialization function // ///////////////////////////// ///////////////////////////////////////////////////////////////// // Function name: PCI_Config_ModeInit // Function: Sets initialization of PCI-IDE ASIC board. // Argument: None // Return value: None // // void PCI_Config_ModeInit(void) { UWORD ConfigAddress; UWORD ConfigData; ////////////////////////////// // Setting of PCI functions // ////////////////////////////// ConfigAddress = 0x40000004; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 1 (000001b) // -> Status / Command // bit 01-00 : 00b (fixed) ConfigData = 0x02000145; // bit 26-25 : DEVSEL timing = 01b (medium fixed) // bit // bit 8 : SERR Enable = 1b : Output pci_serr. 6 : Parity Error Response = 1b : Output pci_serr Application Note U17121EJ1V1AN // Transfer address // Number of transfer bytes // Next table address // // // // // // // Details: Sets handling of interrupts and errors, coding and // then resets IDE bus. ///////////////////////////////////////////////////////////////// 81 CHAPTER 5 APPLICATION EXAMPLES // // bit // bit when Parity Error is detected. 2 : Bus Master = 1b : Enable PCI Bus Master transfer 0 : IO Space = 1b : Enable IO access to PCI-IDE ASIC board PCI_ConfigWrite(ConfigAddress, ConfigData); //////////////////////////// // Setting DES to disable // //////////////////////////// ConfigAddress = 0x40000058; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 22 (010110b), // // -> IDE Bus Master Control (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) // IDE Bus Master Control // Disable DES (Set bit16 des_on to 0) ConfigData = PCI_ConfigRead(ConfigAddress); PCI_ConfigWrite(ConfigAddress, ConfigData & 0xFFFEFFFF); /////////////////////////////////////////// // Setting of Interrupt Control register // /////////////////////////////////////////// *IDEREG_INTERRUPT_CONTROL &= 0xFFFCFFFF; // bit // bit 17 : PCI Bus Master End Interrupt Mask = 0b (Interrupt enabled) 16 : PCI I/F Interrupt Mask = 0b (Interrupt enabled) //////////////////////////////////////// // Setting of Device Command register // //////////////////////////////////////// *IDEREG_DEVICE_CONTROL = 0x00; // bit 2 : nIEN = 0b (Set INTRQ signal to enable) /////////////////// // IDE Bus reset // /////////////////// ConfigAddress = 0x40000044; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 17 (010001b), // // -> IDE Reset Register (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) 82 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES ConfigData = 0x00000001; // bit // 0 : IDE I/F RESET Port = 1b : Output IDE RESETX signal output to IDE I/F. PCI_ConfigWrite(ConfigAddress, ConfigData); return; } //////////////////////////////////// // Transfer mode setting function // //////////////////////////////////// ///////////////////////////////////////////////////////////////////////// // Function name: Set_Transfer_Mode // Function: Setting of transfer mode // Argument: dev_num : Device selection (0:Master/1:Slave) // // // // // // // int Set_Transfer_Mode(int dev_num, UBYTE mode) { status = ATA_Set_Features(dev_num, 0x03, mode); return status; } ///////////////////////////////////////////////////////////////// // Function name: Set_PIO_Timing // Function: Setting of PIO Timing register // Argument: pio_timing : Value set to PIO Timing register // Return value: None // void Set_PIO_Timing(UWORD pio_timing) { UWORD ConfigAddress; UWORD ConfigData; ConfigAddress = 0x40000048; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b Application Note U17121EJ1V1AN // // // // // // // // // // // mode : Transfer mode STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // Return value: ///////////////////////////////////////////////////////////////////////// // // // // // ///////////////////////////////////////////////////////////////// 83 CHAPTER 5 APPLICATION EXAMPLES // bit 07-02 : Register number = 18 (010010b) // -> PIO Timing (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) PCI_ConfigWrite( ConfigAddress, pio_timing ); return; } ///////////////////////////////////////////////////////////////////////// // Function name: Set_UDMA_Timing // Function: Setting of UltraDMA Timing1, 2 registers // Argument: udma_timing1 : Value set to UltraDMA Timing1 register // // void Set_UDMA_Timing(UWORD udma_timing1, UWORD udma_timing2) { UWORD ConfigAddress; UWORD ConfigData; ConfigAddress = 0x4000004C; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 19 (010011b) // // -> UltraDMA Timing1 (In the case of PCI-IDE ASIC board used in this application) udma_timing2 : Value set to UltraDMA Timing2 register // Return value: None // // // // // // ///////////////////////////////////////////////////////////////////////// // bit 01-00 : 00b (fixed) PCI_ConfigWrite( ConfigAddress, udma_timing11 ); ConfigAddress = 0x40000050; // bit 31-11 : IDSEL specification = 010000000000000000000b // Select PCI device connected to AD30 // bit 10-08 : Function number = 00b // bit 07-02 : Register number = 20 (010100b) // // -> UltraDMA Timing2 (In the case of PCI-IDE ASIC board used in this application) // bit 01-00 : 00b (fixed) PCI_ConfigWrite( ConfigAddress, udma_timing2 ); return; } //////////////////////////////////// 84 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES // ATA command execution function // //////////////////////////////////// ///////////////////////////////////////////////////////////////////////// // Function name: ATA_Set_Features // Argument: dev_num : Device selection (0:Master/1:Slave) // Return value: // // // // // // int ATA_Set_Features(int dev_num, int sub_cmd, int mode) { int status; ATA_COMMAND ac; ac.features ac.sector_count ac.cylinder_low ac.device_head ac.command = sub_cmd; = mode; = 0x00; = dev_num<<4; = 0xEF; // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Device/Head register // Command register STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // Function: Executes SET FEATURES command (Protocol:ND, Command:EFh). // ///////////////////////////////////////////////////////////////////////// ac.sector_number = 0x00; ac.cylinder_high = 0x00; status = ATA_PIO_nondata(&ac); return status; } ////////////////////////////////////////////////////////////////////////// // Function name: ATA_Idle_Immediate // Argument: dev_num : Device selection (0:Master/1:Slave) // Return value: // // // // // // int ATA_Idle_Immediate(int dev_num) { ATA_COMMAND ac; STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // Function: Executes IDLE IMMEDIATE command (Protocol:ND, Command:E1h).// ////////////////////////////////////////////////////////////////////////// Application Note U17121EJ1V1AN 85 CHAPTER 5 APPLICATION EXAMPLES ac.features ac.sector_count ac.sector_number ac.cylinder_low ac.cylinder_high ac.device_head ac.command = 0x00; = 0x00; = 0x00; = 0x00; = 0x00; = dev_num<<4; = 0xE1; // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Device/Head register // Command register status = ATA_PIO_nondata(&ac); return status; } /////////////////////////////////////////////////////////////////////////// // Function name: ATA_Identify_Device // Argument: dev_num : Device selection (0:Master/1:Slave) // // // // // // // int ATA_Identify_Device(int dev_num, void *buff) { ATA_COMMAND ac; int status; ac.features ac.sector_count ac.sector_number ac.cyliner_low ac.cylinder_high ac.dev_head ac.command = 0x00; = 0x00; = 0x00; = 0x00; = 0x00; = dev_num << 4; = 0xEC; // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Device/Head register // Command register buff : Buffer pointer STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // Return value: // // // // // // // // // // // Function: Executes IDENTIFY DEVICE command (Protocol:PI, Command:ECh).// /////////////////////////////////////////////////////////////////////////// status = ATA_PIO_datain(&ac, 1, buff); return status; } ////////////////////////////////////////////////////////////////////////// // Function name: ATA_Read_Sector // Application Note U17121EJ1V1AN 86 CHAPTER 5 APPLICATION EXAMPLES // Function: Executes READ SECTOR(S) command (Protocol:PI, Command:20h).// // Argument: dev_num : Device selection (0:Master/1:Slave) // // // // // // // // // int ATA_Read_Sector(int dev_num, UWORD lba, UHWORD sec_cnt, void *buff) { int status; ATA_COMMAND ac; ac.features ac.sector_count ac.cylinder_low ac.device_head ac.command = 0x00; = sector_count; = (lba>>8 & 0xFF); // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Command register lba : LBA sec_cnt : Number of sectors buff : Buffer pointer STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // // // Return value: ////////////////////////////////////////////////////////////////////////// ac.sector_number = (lba & 0xFF); ac.cylinder_high = (lba>>16 & 0xFF); = 0x20; = 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register status = ATA_PIO_datain(&ac, sec_cnt, buff); return status; } /////////////////////////////////////////////////////////////////////////// // Function name: ATA_Write_Sector // Argument: dev_num : Device selection (0:Master/1:Slave) // // // // // // // // // // int ATA_Write_Sector(int dev_num, UWORD lba, UHWORD sec_cnt, void *buff) { Application Note U17121EJ1V1AN // // // // // // // // // // // // // // Function: Executes WRITE SECTOR(S) command (Protocol:PO, Command:30h).// lba : LBA sec_cnt : Number of sectors buff : Buffer pointer STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // Return value: /////////////////////////////////////////////////////////////////////////// 87 CHAPTER 5 APPLICATION EXAMPLES int status; ATA_COMMAND ac; ac.features ac.sector_count ac.cylinder_low ac.device_head ac.command = 0x00; = sector_count; = (lba>>8 & 0xFF); // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Command register ac.sector_number = (lba & 0xFF); ac.cylinder_high = (lba>>16 & 0xFF); = 0x30; = 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register status = ATA_PIO_dataout(&ac, sec_cnt, buff); return status; } ///////////////////////////////////////////////////////////////////////// // Function name: ATA_Read_DMA // Function: Executes READ DMA command (Protocol:DM, Command:C8h). // Argument: dev_num : Device selection (0:Master/1:Slave) // // // // // // // // // // int ATA_Read_DMA(int dev_num, UWORD lba, UHWORD sec_cnt) { int status; ATA_COMMAND ac; ac.features ac.sector_count ac.cylinder_low ac.device_head ac.command = 0x00; = sector_count; = (lba>>8 & 0xFF); // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Command register lba : LBA sec_cnt : Number of sectors STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_TIMEOUT_BMEND : BM timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // // // // // // Return value: ///////////////////////////////////////////////////////////////////////// ac.sector_number = (lba & 0xFF); ac.cylinder_high = (lba>>16 & 0xFF); = 0xC8; = 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register status = ATA_DMA(&ac); return status; } 88 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////// // Function name: ATA_Write_DMA // Function: Executes WRITE DMA command (Protocol:DM, Command:CAh). // Argument: dev_num : Device selection (0:Master/1:Slave) // // // // // // // // // // int ATA_Write_DMA(int dev_num, UWORD lba, UHWORD sec_cnt) { int status; ATA_COMMAND ac; ac.features ac.sector_count ac.cylinder_low ac.device_head ac.command = 0x00; = sector_count; = (lba>>8 & 0xFF); // Features register // SectorCount register // SectorNumber register // CylinderLow register // CylinderHigh register // Command register lba : LBA sec_cnt : Number of sectors STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_TIMEOUT_BMEND : BM timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // // // // // // Return value: ///////////////////////////////////////////////////////////////////////// ac.sector_number = (lba & 0xFF); ac.cylinder_high = (lba>>16 & 0xFF); = 0xCA; = 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register status = ATA_DMA(&ac); return status; } ///////////////////////////////// // Protocol execution function // ///////////////////////////////// ///////////////////////////////////////////////////////////////////////// // Function name: ATA_Device_Selection // Function: Executes device selection protocol. // Argument: dev_num : (0:Master / 1:Slave) // Return value: // // // int ATA_Device_Selection(int dev_num) { Application Note U17121EJ1V1AN // // // // // // // STATUS_SUCCESS : Normal end STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end ///////////////////////////////////////////////////////////////////////// 89 CHAPTER 5 APPLICATION EXAMPLES int status; status = Wait_IDE_BSY0_DRQ0(); if ( status != 0 ) { return STATUS_TIMEOUT_BSY0_DRQ0; } *IDEREG_DEVICE_HEAD = dev_num << 4; wait(TIMER400ns); status = Wait_IDE_BSY0_DRQ0(); if ( status != 0 ) { return STATUS_TIMEOUT_BSY0_DRQ0; } return STATUS_SUCCESS; } ///////////////////////////////////////////////////////////////////////// // Function name: ATA_PIO_datain // Function: Executes PIO data in command protocol. // Argument: atacom : ATA_COMMAND structure pointer // // // // // // // // sector_count : Number of sectors buff : Buffer pointer STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // // // // Normal end // Timeout error end // Device selection // Wait 400 ns // Wait until BSY=0, DRQ=0 // Timeout error end // Wait until BSY=0, DRQ=0 // Return value: ///////////////////////////////////////////////////////////////////////// int ATA_PIO_datain(ATA_COMMAND *atacom, UHWORD sector_count, void *buff) { UBYTE dev, idestat; UWORD *buffp; int i, j, status; buffp = (UWORD*)buff; dev = ( atacom->device_head >> 4 ) & 1; status = ATA_Device_Selection(dev); if ( status != 0 ) { return STATUS_TIMEOUT_DEVICE_SELECTION; } *IDEREG_FEATURES *IDEREG_SECTOR_COUNT = atacom->features; = atacom->sector_count; // Features register // SectorCount register // DEVICE SELECTION timeout // DEVICE SELECTION 90 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES *IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register *IDEREG_CYLINDER_LOW = atacom->cylinder_low; // CylinderLow register *IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register status = Wait_IDE_DRDY1(); if ( status != 0 ) { return STATUS_TIMEOUT_DRDY1 } *IDEREG_COMMAND = atacom->command; wait(TIMER400ns); for ( i=0; i // Loop until DRDY=1 // DRDY1 timeout // Command register // Wait 400 ns // Wait for INTRQ assert // INTRQ timeout error // Status register read (INTRQ clear) // Data read // Alt Status register empty read // Status register read // Error end (after command execution) // Normal end // // // // // // // // // // // // // Return value: 91 CHAPTER 5 APPLICATION EXAMPLES // // ///////////////////////////////////////////////////////////////////////// int ATA_PIO_dataout(ATA_COMMAND *atacom, UHWORD sector_count, void *buff) { UBYTE dev, idestat; UWORD *buffp; int i, j, status; buffp = (UWORD*)buff; dev = ( atacom->device_head >> 4 ) & 1; status = ATA_Device_Selection(dev); if ( status != 0 ) { return STATUS_TIMEOUT_DEVICE_SELECTION; } *IDEREG_FEATURES *IDEREG_SECTOR_COUNT *IDEREG_CYLINDER_LOW = atacom->features; = atacom->sector_count; = atacom->cylinder_low; // Features register // SectorCount register // CylinderLow register // DEVICE SELECTION timeout // DEVICE SELECTION *IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register *IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register status = Wait_IDE_DRDY1(); if ( status != 0 ) { return STATUS_TIMEOUT_DRDY1; } *IDEREG_COMMAND = atacom->command; wait(TIMER400ns); status = Wait_IDE_BSY0_DRQ0(); if ( status != 0 ) { return STATUS_TIMEOUT_BSY0_DRQ0; } for ( i=0; i Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES return STATUS_IDE_ERROR(*IDEREG_ERROR); } return STATUS_SUCCESS; } // Error end (after command execution) // Normal end ///////////////////////////////////////////////////////////////////////// // Function name: ATA_PIO_nondata // Function: Executes PIO non data command protocol. // Argument: atacom : ATA_COMMAND structure pointer // Return value: // // // // // // int ATA_PIO_nondata(ATA_COMMAND *atacom) { int status; UBYTE dev, idestat; dev = ( atacom->device_head >> 4 ) & 1; status = ATA_Device_Selection(dev); if ( status != 0 ) { return STATUS_TIMEOUT_DEVICE_SELECTION; } *IDEREG_FEATURES *IDEREG_SECTOR_COUNT *IDEREG_CYLINDER_LOW = atacom->features; = atacom->sector_count; = atacom->cylinder_low; // Features register // SectorCount register // CylinderLow register // DEVICE SELECTION timeout // DEVICE SELECTION STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // ///////////////////////////////////////////////////////////////////////// *IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register *IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register status = Wait_IDE_DRDY1(); if ( status != 0 ) { return STATUS_TIMEOUT_DRDY1; } *IDEREG_COMMAND = atacom->command; wait(TIMER400ns); status = Wait_IDE_INTRQ(); if ( status != 0 ) { return STATUS_TIMEOUT_INTRQ; } // INTRQ timeout error // Command register // Wait 400 ns // Wait for INTRQ assert // DRDY timeout // Loop until DRDY=1 Application Note U17121EJ1V1AN 93 CHAPTER 5 APPLICATION EXAMPLES idestat = *IDEREG_ALT_STATUS; idestat = *IDEREG_STATUS; if ( idestat & IDEREG_ERROR_ERR_BIT ) { return STATUS_IDE_ERROR(*IDEREG_ERROR); } return STATUS_SUCCESS; } // Alt Status register empty read // Status register read // Error end (after command execution) // Normal end ///////////////////////////////////////////////////////////////////////// // Function name: ATA_DMA // Function: Executes DMA command protocol. // Argument: atacom : ATA_COMMAND structure pointer // Return value: // // // // // // // // int ATA_DMA(ATA_COMMAND *atacom) { int status; UBYTE dev, idestat; dev = ( atacom->device_head >> 4 ) & 1; status = ATA_Device_Selection(dev); if ( status != 0 ) { return STATUS_TIMEOUT_DEVICE_SELECTION; } *IDEREG_FEATURES *IDEREG_SECTOR_COUNT *IDEREG_CYL_LOW *IDEREG_CYL_HIGH = atacom->features; = atacom->sector_count; = atacom->cylinder_low; // Features register // SectorCount register // CylinderLow register // DEVICE SELECTION timeout // DEVICE SELECTION STATUS_SUCCESS : Normal end STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end STATUS_TIMEOUT_INTRQ : INTRQ timeout error end STATUS_TIMEOUT_BMEND : BM timeout error end STATUS_IDE_ERROR : Error end after command execution // // // // // // // // // // // // ///////////////////////////////////////////////////////////////////////// *IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register = atacom->cylinder_high; // CylinderHigh register // Loop until DRDY=1 // DRDY timeout status = Wait_IDE_DRDY1(); if ( status != 0 ) { return STATUS_TIMEOUT_DRDY1; } *IDEREG_COMMAND = atacom->command; // Command register 94 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES wait(TIMER400ns); idestat = *IDEREG_ALT_STATUS; *IDEREG_BUSMASTER_START_STOP |= 0x01; status = Wait_IDE_BMEND(); if ( status != 0 ) { return STATUS_TIMEOUT_BMEND; } status = Wait_IDE_INTRQ(); if ( status != 0 ) { return STATUS_TIMEOUT_INTRQ; } idestat = *IDEREG_ALT_STATUS; idestat = *IDEREG_STATUS; if ( idestat & IDEREG_ERROR_ERR_BIT ) { return STATUS_IDE_ERROR(*IDEREG_ERROR); } return STATUS_SUCCESS; } // Wait 400 ns // Alt Status register empty read // Bus Master Start // BMEND timeout error end // Wait for INTRQ assert // INTRQ timeout error end // Alt Status register empty read // Status register read // Error end (after command execution) // Normal end ///////////////////////////////////////////////////////////////// // Function name: ATA_Soft_Reset // Function: Performs software reset. // Argument: None // Return value: // // // int ATA_soft_reset(void) { int status; *IDEREG_DEVICE_CONTROL = 0x04; wait(TIMER5ms); *IDEREG_DEVICE_CONTROL = 0x00; wait(TIMER5ms); status = Wait_IDE_BSY0(); if ( status != 0 ) { return STATUS_TIMEOUT_BSY0; } return STATUS_SUCCESS; } // Timeout error end // Reset execution // Wait 5 ms // Reset release // Wait 5 ms // Wait until BSY=0 STATUS_SUCCESS : Normal end STATUS_TIMEOUT_BSY0 : BSY=0 timeout error end // // // // // // // ///////////////////////////////////////////////////////////////// Application Note U17121EJ1V1AN 95 CHAPTER 5 APPLICATION EXAMPLES ///////////////////////////////////////////////////////////////////////////////// // Function name: main // Function: Accesses IDE HDD via PCI bus and PCI-IDE ASIC board. // Argument: None // Return value: 0: Normal end // Overview: Issues IDLE IMMEDIATE, IDENTIFY DEVICE, SET FEATURE, READ // // SECTOR(S), WRITE SECTOR(S), READ DMA, and WRITE DMA commands. // // // // // // // ///////////////////////////////////////////////////////////////////////////////// int main(void) { int status; UBYTE wbuff[4096], rbuff[4096]; DISCRIPTOR_TABLE* dsc_tbl; /////////////////////////// // System initialization // /////////////////////////// // Initializes PCI Host Bridge Macro. PCI_HBM_Init(); // Sets initialization of PCI-IDE ASIC board. PCI_Config_BaseAddressInit(); PCI_Config_ModeInit(); ATA_soft_reset(void); // Soft reset ////////////////////////////////// // Issue ATA command to IDE HDD // ////////////////////////////////// //////////////////// // IDLE IMMEDIATE // //////////////////// ATA_Idle_Immediate(0); ///////////////////// // IDENTIFY DEVICE // ///////////////////// ATA_Identify_Device( 0, buff ); ////////////////////////////// // PIO transfer preparation // ////////////////////////////// // Issues IDENTIFY DEVICE command. // Master Device // Buffer storing results // Issues IDLE IMMEDIATE command. 96 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES // Sets transfer mode to PIO transfer Mode0 using SET_FEATURE command. Set_Transfer_Mode(0, PIO_MODE0); // Sets PIO Timing register of configuration register of // PCI-IDE ASIC board. Set_PIO_Timing(IDE_PIO_TIMING_IDE33MHz_MODE0); // Buffer initialization InitBuffer(wbuff, 4096); ////////////////// // PIO transfer // ////////////////// ATA_Write_Sector( 0, 0, 1, wbuff ); ATA_Read_Sector( 0, 0, 1, rbuff ); status = memcmp(wbuff, rbuff, 512); if ( status != 0 ) { printf("Verify Error!: WRITE SECTOR(S), READ SECTOR(S)\n"); } /////////////////////////////////// // UltraDMA transfer preparation // /////////////////////////////////// // Sets transfer mode to UltraDMA transfer Mode0 using SET_FEATURE command. Set_Transfer_Mode(0, UDMA_MODE0); // Sets UltraDMA Timing1 and UltraDMA Timing2 registers of configuration // register of PCI-IDE ASIC board. Set_UDMA_Timing(IDE_UDMA_TIMING1_IDE33MHz_MODE0, IDE_UDMA_TIMING2_IDE33MHz_MODE0); //////////////////////////////// // PCI->IDE UltraDMA transfer // //////////////////////////////// // Sets descriptor table referenced by PCI-IDE ASIC board during UltraDMA transfer. dsc_tbl = (DISCRIPTOR_TABLE*)(BASE_ADDRESS_SDRAM + 0x02000000) Application Note U17121EJ1V1AN // Issues WRITE SECTOR command. // Master Device // LBA 0 // 1 Sector // Buffer storing written contents // Issues READ SECTOR command. // Master Device // LBA 0 // 1 Sector // Buffer storing read results 97 CHAPTER 5 APPLICATION EXAMPLES dsc_tbl->transfer_address dsc_tbl->transfer_byte dsc_tbl->next_table_address = BASE_ADDRESS_SDRAM; = 0x1000; = 0x00000001; // = 4096byte = 8Sector // Last table *IDEREG_DSCTBL_START_ADDRESS = dsc_tbl; // Sets transfer direction of UltraDMA transfer. *IDEREG_BUSMASTER_START_STOP &= 0xFFFFFEFF; // Buffer initialization InitBuffer((UBYTE*)dsc_tbl->transfer_address, 512*8); // Issues command of UltraDMA transfer. ATA_Write_DMA( 0, 0, 8, ); //////////////////////////////// // PCI<-IDE UltraDMA transfer // //////////////////////////////// // Sets descriptor table referenced by device during UltraDMA transfer. dsc_tbl->transfer_address dsc_tbl->transfer_byte dsc_tbl->next_table_address = BASE_ADDRESS_SDRAM + 0x01000000; = 0x1000; = 0x00000001; // = 4096byte = 8Sector // Last table // Master Device // LBA 0 // 8 Sector // Ultra DMA (PCI->IDE) *IDEREG_DSCTBL_START_ADDRESS = dsc_tbl; // Sets transfer direction of UltraDMA transfer. *IDEREG_BUSMASTER_START_STOP |= 0x00000100; // Issues command of UltraDMA transfer. ATA_Read_DMA( 0, 0, 8, ); status = memcmp( (UBYTE*)(BASE_ADDRESS_SDRAM), (UBYTE*)(BASE_ADDRESS_SDRAM+0x01000000), 512*8); if ( status != 0 ) { printf("Verify Error!: WRITE DMA, READ DMA\n"); } return 0; } // Master Device // LBA 0 // 8 Sector // Ultra DMA (PCI<-IDE) 98 Application Note U17121EJ1V1AN CHAPTER 5 APPLICATION EXAMPLES Figure 5-6. IDE_Write_DMA Function 700 0000H 6FF FFFFH : Number of transfer bytes 0000 1000H 0400 0000H 600 0000H Transfer address 5FF FFFFH 500 0000H 4FF FFFFH 400 0000H 3FF FFFFH WRITE DMA (Data transfer from SDRAM to IDE HDD) Bus master transfer of 8 sectors (4096 bytes) is performed from 400 0000H (SDRAM area) to LBA0 of IDE HDD. Descriptor table IDE HDD 4096 bytes 000 0000H Figure 5-7. IDE_Read_DMA Function 700 0000H 6FF FFFFH : Number of transfer bytes 0000 1000H 0500 0000H 600 0000H Transfer address 5FF FFFFH 500 0000H 4FF FFFFH 400 0000H 3FF FFFFH READ DMA (Data transfer from IDE HDD to SDRAM) Bus master transfer of 8 sectors (4096 bytes) is performed from LBA0 of IDE HDD to 500 0000H (SDRAM area). Descriptor table 4096 bytes IDE HDD 000 0000H Application Note U17121EJ1V1AN 99 |
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